A low jitter(≤100fs) clock generator or PLL ,i need

In my project,

1)ADC is AD9208

2)sample clock=3GHz

3) external refclk is 10MHz

4)use a PLL/CLOCK to generate the sample clock

5)Fin=2.1GHz,SNR=54.19dBFS

6)to implement SNR performance,i use Virtual Eval Tool - BETA ,the external min jitter is 100fs.

so,help me choose a low jitter pll/clock to implement SNR performance

and,if i choose ADF4351,can it do that?If cannot, recommend some other PLL/CLOCK

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  • 0
    •  Analog Employees 
    on Aug 19, 2021 12:43 PM

    Hi,

    What is the integration interval requirement for 100fs jitter? It seems nearly impossible to achieve this goal with ADF4351 and 10 MHz reference clock. 

    I would suggest you to select a higher frequency reference clock so that you can use a higher PFD and get a better in-band noise with any PLL. 

    You can use ADISIMPLL to simulate different PLLs to achieve 100 fs requirement. Again, if possible, select higher reference frequency. 

    Let me know if you need any help with ADISIMPLL or selecting part after determining your integration interval.

    Regards,

    Kudret

Reply
  • 0
    •  Analog Employees 
    on Aug 19, 2021 12:43 PM

    Hi,

    What is the integration interval requirement for 100fs jitter? It seems nearly impossible to achieve this goal with ADF4351 and 10 MHz reference clock. 

    I would suggest you to select a higher frequency reference clock so that you can use a higher PFD and get a better in-band noise with any PLL. 

    You can use ADISIMPLL to simulate different PLLs to achieve 100 fs requirement. Again, if possible, select higher reference frequency. 

    Let me know if you need any help with ADISIMPLL or selecting part after determining your integration interval.

    Regards,

    Kudret

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