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HMC7044 PLL1 is not lock

Hi

I have a problem when I use HMC7044. My reference clock is 10MHz,VCXO is 122.88MHz,I set R1 Divider is 125 and N1 Divider is 1536,the PD1 Frequency is 80kHz.

I found my PLL1 is not lock(read register 0x007c is 0x19).

My PLL1 loop filter is follow

When I try follow this,I found something strange 

1.I changed my reference clock to 20MHz,I set R1 Divider is 250 and N1 Divider is 1536,the PD1 Frequency is also 80kHz.,I dound it locked.

2..I changed my reference clock to 20MHz,I set prescalers to 2 (register  0x001F set to 0x02),I set R1 Divider is 125 and N1 Divider is 1536,the PD1 Frequency is also 80kHz.I found it unlocked.

3.I try to changed different  reference clock,and set different R1 Divider and N1 Divider,I found when my eference clock below 12.288MHz,PLL1 will alway unlocked.

I don't kown why I set same PD1 Frequency,the PLL1 status is difference. And how I use 10MHz reference clock to set PLL1 locked