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Clock and Timing

Q&A LTC6954 Clk-Input: Inverting LVDS Signals for Efficient PCB Layout

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Arni on Jun 29, 2021

I use a 200 MHz oscillator with an LVDS output for the input clock of the LTC6954. For efficient PCB layout, I would prefer to invert the LVDS signals (LVDS_P goes to In-, LVDS_N to In+).

Is this possbile or may it lead to a degradation of the jitter performance?

0 ChrisPearson

on Jul 19, 2021 2:41 PM
Yes, this is possible and will not degrade jitter.

If you are setting all the LTC6954 dividers = 1, then it should work great

If you are using any of the LTC6954 EZSync features, that involve stopping the input reference at a differential low, then make sure to take this into account?
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