Post Go back to editing

HMC7044(HMC7043) spurious of finput/2

I have a question about the divider in the "output channel" of HMC7044(HMC7043).
The Condition:
  Input external clock to FIN pin and select External VCO.
  The external clock frequency(fin) : 2.4GHz, +6dBm
  Output MUX selection : Channel Divider Output
  Corse Digital Delay .. OFF, Channel Divider Ratio .. 1

The image of fin/2(1.2GHz, -42.15dB) appears in the above condition.

When I change Output MUX Selection to "fundamental", this image is drastically reduced (< -66.17dB).

This fin/2 image increases the spurious for High-Speed ADC(AD9689) and our customer should reduce this image but he needs delay function too.

Q1. What is the cause of this fin/2 image when the divider set to 1?
      (Our customer wants to know the mechanism of occurring f/2 image.)
Q2. Do you have a workaround to reduce this fin/2 image while using the divider on divide ratio=1?

Best regards,


Parents Reply
  • Hello Kudret,

    You measured -55dBc is 7~10dB lower than I have gotten.
    I measured using the evaluation board of HMC7044.
    Did you measure it using evaluation board?
    I'd like to know the difference of the supply decoupling that you mentioned, could you please describe the difference that you think?

    > I also consulted to a colleage and it is expected to see spurious signal as div1 block uses a logic that depends on div2 function.
    All right. I thought it might be so.

    Best regards,