clock input of AD9523-1 Evaluation Board

Hi,

I would like to create a network sensor sharing same clock (38.4 MHZ using ASTXR-12-38.400MHZ-513501).

Is it possible to use "AD9523-1 Evaluation Board" to duplicate the external clock( ASTXR-12-38.400MHZ-513501) on several channels to provide as a source clock of the same frequency to multiple sensor cards. The ASTXR crystal provides a DC coupled clipped sin-wave signal.

In addition, what frequency signal should I use for the OSC_IN input on the EVB?  Is the same clock will  be sufficient or should I use a higher frequency ?

Regards,

Hani

  • 0
    •  Analog Employees 
    on Jun 2, 2021 6:39 PM

    HI,

    the easiest approach is to apply the TCXO output to the OSC_IN pin and use only the PLL2 to provide all the 38.4MHz outputs.

    I looked on the TCXO data sheet you want to use. The high voltage level is 0.8V, which means the common mode is 0.4V. This is below the common mode voltage the AD9523-1 expects at OSC_IN pin (1.025V to 1.475V), so you need to ac couple the TCXO output.

    AD9523_1_setup_20210602.zipAttached is a quick stp configuration file I put together to give you the PLL2 parameters and the output divider. I did not try it on an evaluation board but it should work.

    This approach creates outputs that have the characteristics of the PLL2 VCO above the PLL2 bandwidth (around 500kHz). Below PLL2 bandwidth they should be a combination of the 38.4MHz you apply and the chip. Use the ADIsimCLK to get an idea.

    The more complicated approach is to procure a VCXO with 348.4*4=153.6MHz and apply the 38.4MHz to REFA or REFB. But this is only if you are concerned about the phase noise of the outputs because this approach creates outputs that have the phase noise characteristics of the VCXO and of the chip below the PLL2 bandwidth and so REFA is "cleaned". If you use lower frequency VCXO (i.e. 76.8M or even 38.4M), this would make for higher phase noise at the outputs because the PLL2 frequency divider would be higher.

    Or maybe, depending on how many 38.4MHz outputs you want, what type and if you do not want to improve the phase noise of the TCXO, you can use one of the fan out buffers from our portfolio: https://www.analog.com/en/parametricsearch/10733#/

     Petre

  • Hi Petre,

    Thanks for your response. 

    The first approach that you propose (applying TCXO output to the OSC_IN) seems adapted for our requirement. 

    However, we are looking to get 6 or more duplicated clipped sin-wave signals of our TCXO, what fan out buffer from the provided list in your message you recommend?

    Regards,

    Hani

  • 0
    •  Analog Employees 
    on Jun 8, 2021 2:53 PM in reply to hhani

    Hi,

    if you want to enter with one TCXO output clipped sinewave clock and fan out 6 clocks of the same frequency and phase, please take a look at ADCLK846. It has 6 outputs that can be configured to be LVDS or CMOS. It is a chip that uses 1.8V supply.

    If you want a buffer that is supplied at 3.3V, please look at the ADCLK946. It can output 6 LVPECL clocks.

    Petre 

  • Hi,

    Thanks for your response.

    I will look for this two components,

    Regards,

    hani