Hi, we currently use ad9552 in our project to generate 900MHz lvds clock.
with ad9552 design tool, we could successully configure the registers through spi interface and generate 900MHz lvds clock(frequency confirmed with oscilloscope).
however, there is a serious problem with the lvds output(both out1 and out2), that is, the commom mode voltage of the outp and outn is different.
it should both be 1.25V around, but in reality, outp is 1.13V and outn is 1.35V.
we tried to change the output clock frequency, it seems that the common mode voltage difference between positive and negtive output increases as output clock frequency increases.
And also the Differential Output Voltage Swing decreases as output clock frequency increases. so when the frequecy increases to 900Mhz, the differential voltage is positive all the time(it should be centered at zero voltage, but now it is centered at a positive voltage with minimum voltage around 0.)
we use dc-coupled lvds connection(figure 18 in datasheet rev.E).
we use external ref 20M with xtal floating.
any idea?many thanks.