ad9552 lvds output common voltage problem

Hi, we currently use ad9552 in our project to generate 900MHz lvds clock.

with ad9552 design tool, we could successully configure the registers through spi interface and generate 900MHz lvds clock(frequency confirmed with oscilloscope).

however, there is a serious problem with the lvds output(both out1 and out2), that is, the commom mode voltage of the outp and outn is different.

it should both be 1.25V around, but in reality, outp is 1.13V and outn is 1.35V. 

we tried to change the output clock frequency, it seems that the common mode voltage difference between positive and negtive output increases as output clock frequency increases.

And also the Differential Output Voltage Swing decreases as output clock frequency increases. so when the frequecy increases to 900Mhz, the differential voltage is positive all the time(it should be centered at zero voltage, but now it is centered at a positive voltage with minimum voltage around 0.)

we use dc-coupled lvds connection(figure 18 in datasheet rev.E).

we use external ref 20M with xtal floating. 

any idea?many thanks.

  • 0
    •  Analog Employees 
    on May 10, 2021 5:59 PM

    Hi,

    let's compare your common mode voltage against the specifications table from the page 5 in rev E data sheet:

    The common mode may be anywhere between 1.125V and 1.375V. The voltages you measured, 1.13V and 1.35V are within this range. I do not believe you should expect the same common mode voltage on the P and N pins because the data sheet specifies a max 25mV between the two when the outputs are static. If this creates a problem with the downstream device, use the ac coupling schematic.

    "The differential outputs voltage swing decreases as the output frequency increases".

    If you look at the figure 12 from the data sheet, this is to be expected.

    "when the frequency increases to 900Mhz, the differential voltage is positive all the time(it should be centered at zero voltage, but now it is centered at a positive voltage with minimum voltage around 0.)"

     Did you try setting the output driver to strong? At frequencies that are so high, even the probe may disturb the signal. Make sure the probe has a bandwidth greater than 900MHz.

    Petre

  • Thank you very much for clearing some points.

    The common mode voltage indeed could be anywhere in a range, as DS said, it is between 1.125 and 1.375V. However, the P and N pins common voltage should be same, or as you said, max 25mV, and max 25mV would not cause problem. The real difference we probed is around 250mV as you see, and this will make the receiver cannot detect the clock, since differential swing is of the same significance. 

    as the output signal is clock, so we think the common voltage difference should not changes much compared to static one.

    we have also noticed the output duty cycle, but we think duty cycle should not influence common voltage.

    we have set the drive strength to strong, and this makes the problem a litter better, but the problem still exists, since the common voltage difference between P and N pins does not change.

    B&W,

    ingdxdy

  • 0
    •  Analog Employees 
    on May 12, 2021 3:24 PM in reply to ingdxdy

    Hi,

    I went in the lab and I downloaded the attached stp configuration file into an AD9552 evaluation board:

    AD9552_setup_900M.zip

    I set OUT2 as a LVDS output and I obtained this:

    The LVDS OUT2 strength was set to 7mA. 

    Petre

  • Appreciate it very much for your time testing the board.

    I think you probed the signal after the ac capacitor, could you please probe the signal before the capacitor if convinient?

    anyway, we have decided to redesign the circuit and use ac-coupled connection.

    Thanks again for your help.

    B&W,

    ingdxdy

  • +1
    •  Analog Employees 
    on May 14, 2021 2:36 PM in reply to ingdxdy

    HI,

    I downloaded into the evaluation board the same configuration from before (900MHz at OUT2, LVDS, 7mA).

    I used an active probe, 1GHz bandwidth to measure the clocks before the capacitors C59 and C60.

    The picture above has: Channel 2, green, OUT2 at J5. Channel 3, blue, OUT2B at J6. Channel 3 (magenta) OUT2 measured before C59 with the active probe above. You can see it has an offset of approximately 2V.

    The picture above has the same settings as the previous one, only now the Channel 4 (magenta) is  OUT2B with the probe placed before the C60 capacitor. The offset is approximately 1.9V, a little below the offset of OUT2.

    These numbers are different from the ones in the LVDS section in the data sheet and I believe the reason is the data sheet gives values when the outputs are static.

    Petre