LTC6952 multi-stage


I want to implement multiLTC6952 stages.

The system will be composed by one master stage LTC6952 locked on an external 10MHz.

The master stage provides 5 outputs pair (REF clock - 100MHz & SSRQ PASS THRU) to synchronize 5 systems.

Design :

I want to know if I can do it because Analog devices examples implement only one VCO stage and multi clock distribution stages.

In my design, I must use a VCO in each stage :

1/ Stage 1 : VCO 1GHz locked on an external 10MHz

This stage provide a reference clock at 100MHz (low frequency reference because the 2° stage is at 1m)

2/ Stage 2 : VCO 4GHz locked on a 100MHz reference clock provided by the master LTC6952.

This stage provide JESD204B clocks

Jitter impact ?



  • 0
    •  Analog Employees 
    on May 11, 2021 12:16 PM

    Sorry for the delay.  I'm still catching up on vacation emails. 

    Yes, a 2 stage synchronization scheme with a LTC6952 in stage 1 and 2 is possible.

    The challenge with this is the architecture will be the close in noise (i.e. phase offsets <40kHz).  The reason for this is the quality of the 2nd stage reference will probably limit the phase noise, due to the stage 1 GHz VCO performance.  If you can share the 1GHz VCO performance at 100Hz, 1kHz, 10kHz, 100kHz, 1MHz, 10MHz phase offsets, then I can create some phase noise curves and give you a better answer on the jitter impact.

    With that being said if you are not concerned about the phase offsets <40kHz, then there won't be much jitter impact at phase offsets >40kHz.

  • Sorry for the delay and thank you for your answer.

    You can find in the attached document VCO performances and OCXO (for the reference input).




  • 0
    •  Analog Employees 
    on May 28, 2021 7:43 PM in reply to LRZ31

    Here is the stage 2 comparison.

    If the stage 2 reference input is driven directly by an ideal 100M reference then stage 2 outputs would generate the plot on the left.

    If the stage 2 reference input is driven from the the 1G SAW locked to the stage 1 reference which is then divided down to 100M then stage 2 outputs would generate the plot on the right.  There is some small degradation <10k.

    Both plots shown used a 4GHz output signal.  I used the 4G VCO on the eval board for the VCO.