I have a doubt regarding the AD9576, related with PLL1 CHARACTERISTICS-Table 7, in page 7 of the datasheet. I want to use as input at REF0 a 50 MHz reference. My doubt is with the input frequency specified for the PLL1 Divider and Doubler. There it says that the typical frecuency input for PLL1 Divider and Doubler is 25 MHz, but there is not specification about min or max.
I see that the specification por PFD of PLL1 is from 25MHz to 50MHz, but I do not know if it applies for the PLL1 Divider and Doubler stage.
Can I use the 50 MHz clock as input in the PLL1 Doubler and Divider stage?
a bit more specific
[edited by: JoseForonda at 3:16 AM (GMT -4) on 25 Apr 2021]