PLL1 Characteristics in the AD9576

Hi guys,

I have a doubt regarding the AD9576, related with PLL1 CHARACTERISTICS-Table 7, in page 7 of the datasheet. I want to use as input at REF0 a 50 MHz reference. My doubt is with the input frequency specified for the PLL1 Divider and  Doubler. There it says that the typical frecuency input for PLL1 Divider and Doubler is 25 MHz, but there is not specification about min or max.

I see that the specification por PFD of PLL1 is from 25MHz to 50MHz, but I do not know if it applies for the PLL1 Divider and Doubler stage.

Can I use the 50 MHz clock as input in the PLL1 Doubler and Divider stage?

thank you



a bit more specific
[edited by: JoseForonda at 3:16 AM (GMT -4) on 25 Apr 2021]
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    •  Analog Employees 
    on Apr 26, 2021 6:23 PM

    Hi,

    You should see Table 7 together with reference inputs table 4 at page 6.

    Reference input path section of Table 7 tells you that typically, the frequency at divider or doubler input is 25MHz. So the typ values in the following sections of the table were given for 25M reference.

    The PFD Frequency section tells you that the input frequency to PFD must be between 25MHz and 50MHz. So however you set the divider or the doubler, make sure their output frequency is between 25MHz and 50MHz.

    And if you use a crystal as the frequency source, then Table 4 tells you that the frequency of the crystal for PLL1 must be 25MHz.

    If you use the 50MHz clock at REF2 (CMOS or ac coupled), then you cannot use the doubler because the doubler output is 100MHz and you violate the PFD max frequency of 50 MHz.

    You can divide it down by 2 and you enter in PFD with 25MHz. But this is not recommended because you should enter in the PFD with the highest frequency possible. So I would bypass both the divider and doubler towards PLL1 PFD when REF2=50MHz.

    Petre

  • Hi, Petre. Thank you for answer.

    regarding this I'm not sure that 50MHz would be a valid frequency for REF2, because at page 26 it is said: "REF2 supports frequencies of 8 kHz, 10 MHz, 19.44 MHz, 25 MHz, and 38.88 MHz" . So the max value that can be entered is 38.88MHz, is that correct? or I'm misunderstanding.

    If you use the 50MHz clock at REF2 (CMOS or ac coupled), then you cannot use the doubler because the doubler output is 100MHz and you violate the PFD max frequency of 50 MHz.

    Just to clarify, I'm not thinking in use REF2, I just want to use REF0 with 50MHz and use it to feed both PLLs.

    So, do you think I can enter REF0= 50 MHz for PLL1? 

    thank you for your time and help.

  • +1
    •  Analog Employees 
    on Apr 26, 2021 8:11 PM in reply to JoseForonda

    HI,

    That phrase at page 26 seems to me to state that one can use the listed frequencies. These are frequencies used in the applications listed on the 1st page. I do not interpret them as the only frequencies that can be used.

    You can use REF0=50MHz only as CMOS or differential input (not as a crystal resonator because of table 4 limit of 30.72MHz). Then you have to set the PLL1 divider to 1 in order to meet the PLL1 PFD 50 MHz max frequency.

    On PLL0, you could use the doubler because the PLL0 PFD max frequency is 170MHz or 290MHz (see table 6), but I do not recommend it. The doubler works best with crystal resonators because the duty cycle is 50%. If your 50 MHz source cannot keep the duty cycle at 50%, then the doubler may create problems.

    Petre

  • Thank you for the indications. I think this solve my doubt.

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