AD9544 difficulty in achieving reliable lock w/ 1pps GPS reference.

Objective:  I need to create a variety of clocks that neither gain or lose cycles relative to similarly disciplined clocks at distant locations.  I need a well-disciplined 10 MHz,  44.1kHz and other related sample rate clocks required for system operations.  There are no special synchronizations required between the clocks.

The 1pps GPS reference source has 30ps RMS random jitter, typical of many GPS chip sets.
The System Clock is currently the EVAL board's 52MHz Xtal (x2)

I'm using 50mHz as the DPLL loop bandwidth.  This works as well or better than other settings, and it appears to be the recommended setting for this kind of application.

I currently achieve FLD with some regularity, although not with sufficient alacrity.
I achieve PLD very occasionally, and not for any extended duration.

From reading the other posts and replies here in the EZ, I suspect that the native jitter from the EVAL Board's 52MHz Xtal, exacerbated by the x2 feature, might be the limiting factor.

From previous advise, It appears that two suggestion have been offered:

  1. Use a low jitter TCXO as the system clock, and do not use the x2 feature.
  2. Use an additional stable external reference source to compensate a jittery system clock.

I assume that with an Ultra-low Jitter MEMS XO, for the System Clock, the second approach won't be necessary. 

I figure that anything I might use as an additional stable compensating reference, won't be better than the MEMS XO System Clock.
Please correct me If I'm wrong in this assumption.

The device I'm looking at is a 100MHz MEMS Oscillator for the System Clock.  These are readily available at a reasonable price point.
This device features 1ps RMS Period Jitter, and 0.1 ps RMS random jitter.  This looks pretty good in my estimations.

 Q1:
Am I on the right track?   Recommendations?

It's also possible that I've made some poor choices in my settings, I've attached my current .cso file.

cso file

Q2:
In this related EZ linkpminc48 posted the following:

"… the AD9545 DPLL0 cannot close the loop in 1Hz situations directly. It needs a 1Hz modulation applied to an output onto which to apply a tag to the TDC output. "

Does this apply to my AD9544 application?  If so, I'm not sure that I fully understand.

Thanks in advance to any and all respondents.

-ted



I appended a link to my cso file, as drag drop did not appear to work as expected.
[edited by: Ted_S at 6:55 PM (GMT -4) on 17 Apr 2021]
  • Oops, I misspoke.

    I simply thought I saw an improvement in performance using the Open Loop Compensation from the External Sensor, using the zeroed out default coefficients.  Open loop compensation is not my likely path to performance improvement. 

    The while the documentation on the compensation methods is rather involved, it is rather well written. Complements to the author(s).

    Thx -t