AD9544 difficulty in achieving reliable lock w/ 1pps GPS reference.

Objective:  I need to create a variety of clocks that neither gain or lose cycles relative to similarly disciplined clocks at distant locations.  I need a well-disciplined 10 MHz,  44.1kHz and other related sample rate clocks required for system operations.  There are no special synchronizations required between the clocks.

The 1pps GPS reference source has 30ps RMS random jitter, typical of many GPS chip sets.
The System Clock is currently the EVAL board's 52MHz Xtal (x2)

I'm using 50mHz as the DPLL loop bandwidth.  This works as well or better than other settings, and it appears to be the recommended setting for this kind of application.

I currently achieve FLD with some regularity, although not with sufficient alacrity.
I achieve PLD very occasionally, and not for any extended duration.

From reading the other posts and replies here in the EZ, I suspect that the native jitter from the EVAL Board's 52MHz Xtal, exacerbated by the x2 feature, might be the limiting factor.

From previous advise, It appears that two suggestion have been offered:

  1. Use a low jitter TCXO as the system clock, and do not use the x2 feature.
  2. Use an additional stable external reference source to compensate a jittery system clock.

I assume that with an Ultra-low Jitter MEMS XO, for the System Clock, the second approach won't be necessary. 

I figure that anything I might use as an additional stable compensating reference, won't be better than the MEMS XO System Clock.
Please correct me If I'm wrong in this assumption.

The device I'm looking at is a 100MHz MEMS Oscillator for the System Clock.  These are readily available at a reasonable price point.
This device features 1ps RMS Period Jitter, and 0.1 ps RMS random jitter.  This looks pretty good in my estimations.

 Q1:
Am I on the right track?   Recommendations?

It's also possible that I've made some poor choices in my settings, I've attached my current .cso file.

cso file

Q2:
In this related EZ linkpminc48 posted the following:

"… the AD9545 DPLL0 cannot close the loop in 1Hz situations directly. It needs a 1Hz modulation applied to an output onto which to apply a tag to the TDC output. "

Does this apply to my AD9544 application?  If so, I'm not sure that I fully understand.

Thanks in advance to any and all respondents.

-ted



I appended a link to my cso file, as drag drop did not appear to work as expected.
[edited by: Ted_S at 6:55 PM (GMT -4) on 17 Apr 2021]
Parents
  • 0
    •  Analog Employees 
    on Apr 19, 2021 6:35 PM

    Hi,

    it is not the jitter of the 52 MHz crystal resonator that matters in the 1PPS controls. It is its stability that matters. We recommend to use a 52 MHz crystal resonator  so the outputs of the AD9544 have the best phase noise and a low frequency (10M or 20M) OCXO or TCXO to stabilize the system clock. The behavior you see (FLD with some regularity, PLD very occasionally) shows properly the lack of stability of the system clock.

    If you can or not use the 100M oscillator you talk about: see what stability you need when the 1PPS goes away and the DPLLs enter holdover. Then the default lock thresholds of the AD9544 reference monitor  are  set at 700ps (you can increase them, function of the reference clock jitter). They also dictate the stability of the system clock you need to create.

    In Q2, I wrote that. It is related to internal zero delay cases. I explained it to you in your previous post. It does not seem to apply to you because you seem to not care about the phase relationship between the output clocks and the 1PPS. Usually, people want a phase alignment between  output clocks and the 1PPS and therefore they need to use the Internal Zero Delay mode. 

    I looked over the cso file you sent:

    - you changed the 52MHz crystal frequency to 51.99575MHz. Why? I suppose you play with the AD9544 eval board, and this board has a 52MHz crystal.

    - you apply 1PPS at REFBB. That path has R319=50ohm resistor to ground. See if your 1PPS source needs a 50ohm load. It may not, so you may have to take it out. 

    -analyze REFBB valid status at one of the Mx pins with an oscilloscope, so you make sure the reference is always valid. You do not want the chip to see it valid/invalid because this makes the DPLLs to do in and out of trying to lock

    - the DPLLs are set correctly in phase buildout, with 50mHz bandwidth, because you do not care about the phase alignment between the outputs and 1PPS

    -the outputs are all set to CML, which is good. Just set the jumpers P300 to P304 between pins 1 and 2. If you want to use the HCSL drivers, put the jumpers between pins 2 and 3 and connect a wire between TP307 and TP308 (VOUT_COMMON signal was left floating and it needs to be grounded)

    Petre

  • Thanks for the prompt reply!

    I conflated the parameters of Jitter and Stability.  Thanks for setting me straight.  You indicate that System Clock Jitter is less determinative of performance (in this application) than is Stability which characterizes it's variability over a longer duration, and is fundamentally a function of temperature.

    I suspect that  even small air currents surrounding the System Clock device may have a profound effect on Stability performance.  I've occasionally seen "wind shields" surrounding such components on pc boards, in order to minimize such effects.

    Regardless, the Eval Board's 52MHz Xtal reportedly has an Initial Tolerance of +- 25 ppm, and a Stability of +-25 ppm across a -40 thru 85° C temp range.

    The TC MEMS XO that I was considering is not materially better with regard to Stability, only having a +- 25 ppm specification. This figure is inclusive of Initial Tolerance.  Nice, but not much help.

    Is it also possible that using a MEMS device without the need for the x2 function will be of some benefit?
    Your thoughts?

    Thank you for reviewing my .cso file.   A few notes regarding your bullets.

    • I changed the 52MHz Xtal specification to 51.99575MHz to normalize the free-run 10MHz output. 
      This seems like a much larger initial frequency offset than I would have expected.
       
    • The REFBB Status has been solidly valid.
      Interestingly, Once the above Xtal spec was adjusted, I have been able to reduce the REFBB (1pps) Reference Offset Tolerance down to 1ppm without incident.  Prior to the System Clock spec adjustment, it needed to be >95ppm.
       
    • Thanks for affirming the Phase Buildout  and bandwidth settings.
       
    • The CML outputs allow for convenient probing with my instrumentation, I had considered the HCSL alternative.

    I'm fortunate to have external 10MHz OCXO available from a HP Frequency Counter.  It boasts a Stability rating of 2.5ppb.
    I'll condition that 10MHz reference to drive one of the other reference inputs to stabilize the system clock, then see how we do.

    Most OCXOs are really expensive.  The OCXO specified [ABRACON-AOCJY7TQ-X-100.000MHZ-1] for the Eval Bd is >$800. That's not gonna happen.  I'll be looking for other TCXO options to stabilize the lock performance using the AD9544.

    I'm sure that I will NOT be able to come close to the specs of my 2.5ppb HP device. 
    Any idea of what Stability specs I might need for my application?

    Thanks again for the assistance.  I hope that this posting can help others.

  • 0
    •  Analog Employees 
    on Apr 20, 2021 1:24 PM in reply to Ted_S

    HI,

    Is it also possible that using a MEMS device without the need for the x2 function will be of some benefit?
    Your thoughts?

    Usually the oscillators have a duty cycle that is not exactly 50%. This creates problems when using the doubler. So I do not recommend using the doubler with oscillators. Use the doubler only with crystal resonators.

    Use OCXOs of very low frequency, like 10 MHz. They are much cheaper. Then use the system clock compensation method 3.

    Any idea of what Stability specs I might need for my application?

    You did not say what application you have. I explained in my previous answer how to go about it. This is something you should determine.

    Petre

  • Good advice.  You are correct, 10MHz OCXOs are much less expensive.  Still, they are priced a bit outside the current cost and power profile for this project. 

    It looks like I can achieve 2 orders of magnitude stability improvement using a less costly 10MHz TCXO as a compensating reference.  This is not quite the 4 orders of magnitude stability improvement I might expect from a my external OCXO HP reference, or the 3 orders of magnitude I might get from a modestly priced OCXO.  I may need to reconsider an OCXO, if the lower cost TCXO fails to meet my objectives.

    I have one interesting observation that supports your stability advice.  When I use the compensation method 3, using the external temp sensor, the lock performance is improved.   I believe that the external sensor is thermally coupled to the 52MHz Xtal mounted on the opposite side of the Eval PC board. 

    As expected, little drafts of air across these components cause temporary shifts in my 10MHz output relative to my external OCXO.

    Thanks again.

    -t

  • 0
    •  Analog Employees 
    on Apr 21, 2021 5:30 PM in reply to Ted_S

    Hi,

    you confused me with the external temperature sensor. The compensation method 3 uses a reference clock (not the temp sensor) into the auxiliary DPLL to create the system clock compensation factor. 

    The compensation method 1 uses the internal temperature sensor or a temperature register (in which the controller is supposed to write values read from an external temperature sensor) to calculate a polynomial based compensation factor. I supposed you used this method and I believe it may have compensated some variation of the crystal resonator. But you had to know the polynomial coefficients of the crystal variation with temperature.

    Petre

Reply
  • 0
    •  Analog Employees 
    on Apr 21, 2021 5:30 PM in reply to Ted_S

    Hi,

    you confused me with the external temperature sensor. The compensation method 3 uses a reference clock (not the temp sensor) into the auxiliary DPLL to create the system clock compensation factor. 

    The compensation method 1 uses the internal temperature sensor or a temperature register (in which the controller is supposed to write values read from an external temperature sensor) to calculate a polynomial based compensation factor. I supposed you used this method and I believe it may have compensated some variation of the crystal resonator. But you had to know the polynomial coefficients of the crystal variation with temperature.

    Petre

Children
  • Oops, I misspoke.

    I simply thought I saw an improvement in performance using the Open Loop Compensation from the External Sensor, using the zeroed out default coefficients.  Open loop compensation is not my likely path to performance improvement. 

    The while the documentation on the compensation methods is rather involved, it is rather well written. Complements to the author(s).

    Thx -t