AD9544 Outputs stopped working.

Just getting started here, and I need some assistance.

I’ve made some good early progress, but have somehow lost the ability to see any outputs.
Seems like a noobie problem, but it’s stopped me in my tracks.
What’s more perplexing, is I have had the outputs working, but now none are!

 ACE version: 1.10.2671.1118 w/ AD9544 Eval Bd.

I’m using a single 1pps reference from a GPS receiver. I’m generating a number of disciplined clocks from this.

When the outputs were working, I was able to observe lock behavior.
It was not yet meeting my specification, but so far the performance has been good enough to see the process work.

I’m using the CML single ended output, monitored on a scope.  Monitored this way does not show the cleanest signal, but it’s been more than adequate to see the generated waveforms, from multiple outputs.

I’ve followed the notes previous outlined here. 109964/ad9544-pcbz-help-getting-outputs-working, loading the .cso file, followed by Cal All, Sync All, IO Update tabs.
Still no luck.

I’ve tried every other manipulation that I thought might be useful, to no avail. 

What am I missing?

Attached zipped .cso file :

  • Ok,  I got it working...

    ...after much head-scratching and chin-stroking.

    (I can do both at the same time)

    So this problem started after yesterday's power-down, and today's power-up.

    I was able to get the outputs to function again by disabling the Ref Sync Enable.

    I saved the .cso, with Ref Sync Enable OFF, powered down, and restarted with the updated.cso.
    The eval device now functions as expected..

    BTW, once working, Re-enabling the Ref Sync Enable does not kill the outputs.


    Can anyone help me understand the above?

    Thanks in advance

  • 0
    •  Analog Employees 
    on Apr 12, 2021 2:31 PM in reply to Ted_S


    The Reference synchronization feature works only with the DPLL being set in Internal Zero Delay mode, not with the phase buildout mode you set the DPLLs to function (see page 81 in rev B AD9545 data sheet).  

    So it is hard for me to comment on how the chip behaves with this feature being enabled  when the DPLL is in phase buildout mode.

    Also, I want to give you a heads up: if you want to create 1Hz output aligned to the 1PPS input in Internal Zero Delay mode, refer to AD9545 rev B data sheet, page 86, section Caveat to Internal Zero Delay Operation:

    The AD9544 plugin does not allow tagged feedback rates and users cannot set the AD9544 accordingly.

    My recommendation is for you to reprogram the AD9544 eval board to make the board be seen as an AD9545 board by the PC and have the possibility to use the AD9545 plugin. You can find the USB EEPROM programmer here:

    Reprograming the AD9544 evaluation board to be seen by the PC as an AD9545 evaluation board allows the tools to set the DPLLs in Internal Zero Delay mode with the AD9544 on the board.

    Remove P502 jumper first to allow the EEPROM to be programmed:


  • Thanks for the prompt reply.

    The use of the Reference Synchronization Feature was unclear to me.  I'll try to read up on it when time allows, as the Zero Delay Operation does not appear required for my fairly pedestrian application.

    I've seen the notes regarding the Internal Zero Delay Operation in the EZ.  I believe that this shouldn't be a factor in this design.

    I simply need to create clocks that neither gain or loose cycles relative to similarly disciplined clocks at distant locations. Consequently, the need to align a 1pps out with the 1pps reference is just is not required. The 10 MHz and the ubiquitous 44.1kHz related sample rate clocks are the only ones material to system performance.  The remaining clocks are simply a bonus to support other onboard resources.

    I'm currently working to optimize lock speed and performance. I'm making progress, albeit slow.
    I'll reach out if (or when) I reach an impasse.

    Thanks again.