HMC7044 PLLs not locking


We are using an FMC Card (HTG-FMC-14ADC-16DAC) and I'm trying to configure the register settings of HMC7044 on the card to get the clock output but I can't get the PLLs to get locked.

122.88Mhz clock is input at the OSCIN and CLKIN1 inputs. Even though there's no input at CLKIN0 (pin no. 39,40), HMC7044 is taking "PLL1 Best Clock" and "PLL1 Active CLKINx" as CLKIN0 input (as per value read from register 0x0082). I changed the reference mode switch to "manual" and set the CLKIN priority to be CLKIN1 but still HMC7044 is taking "PLL1 Active CLKINx" as CLKIN0.

I have set the prescaler and dividers for PLL1 such that PD1 is 122.88KHz and enabled doubler and dividers for PLL2 such that PD2 is 50MHz. The register settings are shown below:

{addr, data}

//Global Enable Control
{0x01, 0x64}
{0x03, 0x2f}
{0x05, 0x02}

//PLL1 Registers
{0x14, 0x55}
{0x29, 0x0c}
{0x1d, 0x01} //CLKIN1 Input Prescaler
{0x20, 0x01} //OSCIN Input Prescaler
{0x21, 0xe8} //R1 Divider
{0x22, 0x03}
{0x26, 0xe8} //N1 Divider
{0x27, 0x03}
{0x28, 0x1f}

//PLL2 Registers
{0x32, 0x00}
{0x33, 0x05} //R2 Divider
{0x34, 0x04}
{0x35, 0x3c} //N2 Divider
{0x36, 0x00}

//Restart Dividers/FSM
{0x01, 0x66}
{0x01, 0x64}
{0x01, 0xE4}

I don't understand why it's not selecting CLKIN1 as input for PLL1.

Thank you,

Karthik Bhat

Parents Reply
  • Hi Kudret,

    Yes, the chip was in sleep mode. I only checked for "enable/disable chip" pin and didn't read the one line write up saying GPIO3 was also used for "sleep mode". If only it was mentioned "GPIO3/Sleep" or "GPIO3/Enable" in the "Pin Configuration" figure page 14 of the datasheet, I would have saved a lot of time! I kindly advice this is updated in the datasheet. 

    I'm also not sure why FPGA was driving that pin high by default. Anyways, thank you Kudret I wouldn't have solved this without your help.

    Thank you,