Recently I configure AD9680 and HMC7043 to implement data collection. It's a cascaded structure, a single HMC7043 is at the root node,the other 3 HMC7043s are in parallel at the next level.
The first HMC7043 at second level provides clk and sysref to 6 AD9680s and FPGA1,The second HMC7043 at second level provides clk and sysref to 6 AD9680s and FPGA1,and the third HMC7043 provides GTX bank clock.
Now the problem I met is that the SYNC signal from FPGA to AD9680 is pull down periodically,and I don't know why.The link parameter is LMFSHD=22210,and I pretty sure that I set correctly to the IP core and ad9680.the clock is correct and FD_A from AD9680 seemly correct too, but the ILAS stage is cannot complete transferring and re-transfer BCBC again.The sample rate is 480 Msps,and the coreclk is 240M, the sysref is 15M. I read back from AD9680 that the clock is locked and no setup or hold error.The GPO from HMC7043 is hign when set as the clock output phase status.
So it's really nice and appreciated that if anybody could give me some advice.Thank to your guys...
