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AD9528 - Dual VCXO Option

Hello Clock and Timing Experts,

I need to support two VCXO frequencies using the AD9528. Since the PLL1 Input Receiver Control Register let me select single ended VCXO clock from either negative or positive VCXO_IN pins, I wonder if I can use this to multiplex the two VCXOs.

Figure 25 in the datasheet shows configuration with one single ended CMOS clock, where one of the VCXO_IN inputs is decoupled to GND via a 0.1uF capacitor instead of having this pin floating.

I wonder if my trick would work and I can save PCB space for an additional clock multiplexer?