I am trying to configure the AD9545 (see ACE configuration file in the application).
As a SYSCLK i'm using a quartz resonator (52 MHz,10ppm): ABM13W-52.0000 MHZ-5-NH7U-T5
As a RefA input i'm using an accurate OCXO (20MHz, 20ppb): AOCJYR-20,000 MHZ-M5627LF.
As a RefAA input i'm using 1PPS signal.
Thus, we have a system in which a quartz resonator with an excellent indicator of phase noise is compensated by a very frequency-accurate quartz oscillator.
Moreover, an accurate 1PPS signal comes to DPLL0 and additionally compensates SYSCLK.
The Internal Zero Delay mode is used to synchronize the input PPS with the outputs.
With this configuration, i get the DPLL0 frequency lock in less than 5 seconds.
The phase lock is achieved in ~15 minutes without using Fast Acquisition mode and in ~3 minutes with it.
The main problem is that the phase lock is not stable.
On the oscilloscope (video is in application), I can observe that the divergence of the input PPS and the output signals floats within + - 5ns of the right phase position.
How can I achieve a stable phase lock and phase divergence of the input and output signals of no more than 1ns or less?