Recommended for New Designs
The AD9577 provides a multioutput clock generator function,
along with two on-chip phase-locked loop cores, PLL1 and PLL2,
optimized for network clocking...
AD9577 on Analog.com
I am goning to distribute a common 40 MHz clock to 2 DDSs and 2 ADCs. Will AD9577 work for this purpose? If not, do you have any suggestion?
The ADC needs 5 V CLK and the DDS needs 1.8 V CLK.
the AD9577 is a good choice if the 40 MHz clocks to the AD9913 may not be phase aligned to the 40 MHz clocks to the AD7769.
The AD9577 has two PLLs that are not recommended to work at the same frequency…