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Clock distribution to 2 DDSs (9913) and 2 ADCs (AD7769)

Thread Summary

The user is distributing a 40 MHz clock to 2 DDSs (AD9913) and 2 ADCs (AD7760). The AD9577 is suitable if phase alignment is not required, as it can output LVPECL or LVDS clocks for the AD9913, but it is not recommended to use both PLLs at the same frequency due to degraded jitter performance. For phase alignment, the AD9576 is recommended.
AI Generated Content

Hi,

I am goning to distribute a common 40 MHz clock to 2 DDSs and 2 ADCs. Will AD9577 work for this purpose? If not, do you have any suggestion?

The ADC needs 5 V CLK and the DDS needs 1.8 V CLK.