Hi,
I am goning to distribute a common 40 MHz clock to 2 DDSs and 2 ADCs. Will AD9577 work for this purpose? If not, do you have any suggestion?
The ADC needs 5 V CLK and the DDS needs 1.8 V CLK.
AD9577
Recommended for New Designs
The AD9577 provides a multioutput clock generator function,
along with two on-chip phase-locked loop cores, PLL1 and PLL2,
optimized for network clocking...
Datasheet
AD9577 on Analog.com
Hi,
I am goning to distribute a common 40 MHz clock to 2 DDSs and 2 ADCs. Will AD9577 work for this purpose? If not, do you have any suggestion?
The ADC needs 5 V CLK and the DDS needs 1.8 V CLK.