ADF4002 parameters

Hello

          Customer use 10MHz reference clock to Ref of ADF4002. They would like to get output frequency is 128.88MHz. We help setting these parameters as attached. Has any problem or risk of ADF4002 setting for 128.88MHz ?  

          Another question, if use fractional PLL, has any suggest solution for it ? Thank you.  

https://drive.google.com/file/d/10U7Ze_zawiivSqxNXEBgL6NZaD-N8cK_/view?usp=sharing 

BR

Patrick



Fractional PLL
[edited by: patrickchen@morrihan.com at 2:16 PM (GMT -5) on 5 Feb 2021]
Parents
  • +1
    •  Analog Employees 
    on Feb 10, 2021 10:51 PM 2 months ago

    The ADF4002 is an integer PLL.  Did they want a fractional PLL.  Here is the list the ADIsimPLL came up with for fractional options.

    The decision from here will be based on how good of phase noise vs power dissipation performance they desire vs cost.  Did you have any phase noise rqmts?

  • Hello 

           If customer use ADF4150 for 122.88MHz output frequency to replace ADF4002,is it a suitable fractional PLL solution ?

           Per below schematics, 122.88MHz comes from RF INA for clock output and not comes from RD OUTA/RF OUTB with 122.88MHz VCO.

            Is it ok if not through RF OUTA/ RF OUTB  ? Thank you. 

    BR

    Patrick 

  • Hello

                 Has any suggestion for above question? Thank you. 

    BR

    Patrick

  • +1
    •  Analog Employees 
    on Mar 3, 2021 10:41 PM 1 month ago in reply to patrickchen@morrihan.com

    Patrick,

    The customer is putting 122.88MHz into the RF input.  The RF input's datasheet min is 500MHz.  

  • Hello 

              But per PLL simulation tool, why we can lock 122.88MHz while RF input frequency is 122.88MHz? Which setting we miss it ?   Thank you.

    BR

    Patrick

  • +1
    •  Analog Employees 
    on Mar 4, 2021 10:59 AM 1 month ago in reply to patrickchen@morrihan.com

    Hi Patrick,

    The RFIN frequency (the RF feedback from the VCO) should be between 500MHz and 5000MHz for this part. The PLL can output frequencies lower than this from RFOUT by using its output dividers. ADIsimPLL does not check the minimum frequency of PLLs since it is often not a hard limit. For a lot of our PLLs it is possible to operate slightly below the minimum frequency by ensuring the RFIN signal's slew rate is kept high enough. But operating outside of the datasheet spec table will always come with risks that the specified performance may not be met. So in practice there is a good chance you will not lock with that VCO. 
    If you could get a different VCO and lock PLL at 983.04MHz or 1966.08MHz then use the /8 or /16 stage this would get 122.88MHz and would be within datasheet spec.

    Another concern I have with that particular VCO is that it is a CMOS output, and it is not a 50Ohm output. A square wave input to RFIN is good if you want to run at lower frequencies to keep the slew rate high, but the absolute max rating for RFIN power for ADF4150 is 5dBm or 0.8Vpkpk (assuming 50Ohm system). So I am concerned about the 3.3V input at RFIN without some sort of logic shifting circuit. A voltage divider is most simple but I do not think the current is available to get enough reduction from 3.3V. A resistive divider is also an option but it will be hard to design exact resistor values without knowing the impedance of the RFIN at 122.88MHz. Figure 10 of the ADF4001 datasheet shows an example resistive splitter circuit. A clock buffer is probably the best option, please see here for an example of using a clock buffer at RFIN.

    Regards,

    Alex

  • Hello Alex

                Thank you. So per below topology, we need to do resistor divider to tuning 0.8Vpk to RFIN via R91316/R3404/R476 resistor, right?

                 It is possible not lock to 122.88MHz due to out of datasheet spec. and recommend to use square wave VCO( 983.04MHz or 1966.08MHz) to RFIN then use /8 or /16 stage to RFOUT pin for 122.88MHz, is it correct? 

                 Another question, if we will not use ADF4150 then change to ADF4002 use below same topology , has any risk for design by ADF4002 ? Per my understanding, ADF4002 is integer PLL and cause any side effect to lock 122.88MHz? Thank you. 

    BR
    Patrick

Reply
  • Hello Alex

                Thank you. So per below topology, we need to do resistor divider to tuning 0.8Vpk to RFIN via R91316/R3404/R476 resistor, right?

                 It is possible not lock to 122.88MHz due to out of datasheet spec. and recommend to use square wave VCO( 983.04MHz or 1966.08MHz) to RFIN then use /8 or /16 stage to RFOUT pin for 122.88MHz, is it correct? 

                 Another question, if we will not use ADF4150 then change to ADF4002 use below same topology , has any risk for design by ADF4002 ? Per my understanding, ADF4002 is integer PLL and cause any side effect to lock 122.88MHz? Thank you. 

    BR
    Patrick

Children
  • Hello Alex

               Has any suggestion for above? Thank you. 

    BR

    Patrick

  • +1
    •  Analog Employees 
    on Mar 9, 2021 5:04 PM 1 month ago in reply to patrickchen@morrihan.com

    Hi Patrick,

    I think even with a square wave VCO it will be difficult to get enough slew rate to get the ADF4150 to work with RFIN = 122.88MHz. 

    As mentioned before I think it would be better to find a VCO which could cover 983.04MHz or 1966.08MHz range and use the output divider. If you are at these frequencies then a square wave VCO is not required. In fact a sine wave VCO would probably be better for designing matching network purposes.

    If an integer N PLL will be acceptable, the ADF4002 would be a reasonable choice. You could get 122.88MHz by using a 10MHz reference and a PFD frequency of 640kHz as an example. Are multiple channels required, or just one frequency? With integer N PLLs you will only be able to get channel spacing equal to the PFD frequency. If you are just trying to get one frequency, then integer N PLL is normally a better choice. Simulating with ADIsimPLL is best to make sure the design will meet your phase noise requirements.


    Note, the ADF4002 also has the same issues with interfacing with CMOS RF inputs as noted previously with the ADF4150. So please beware that that VCO you have proposed will also some require way to reduce the VCO signal level. But the ADF4002 as a lower min RF frequency so slew rate will be less of a concern than the ADF4150.

    https://ez.analog.com/rf/f/q-a/73844/adf4001---interfacing-cmos-vcxo-to-rfin


    Regards,

    Alex

  • Hello Alex

        Customer just require one frequency of 122.88MHz so ADF4002 is also suitable for requirement , right? 

         Another question, I know if use VCO (983.04MHz or 1966.08MHz range) and use the output divider is better for ADF4150. But the customer board already gerber out PCB. So 122.28MHz is ensured not locked PLL of ADF4150, right? 

         if We need to modify on board.,

    1. choose another VCO ((983.04MHz or 1966.08MHz )

    2. tuning resistor divider to meet  RFIN signal level

    3. Jump wire from RFOUT to connect 122.88MHz by schematics

    Thank you. 

     

  • +1
    •  Analog Employees 
    on Mar 12, 2021 4:16 PM 1 month ago in reply to patrickchen@morrihan.com

    Hi Patrick,

    If you wanted to go ahead with that board, this might work:

    Find a VCO covering 983.04MHz or 1966.08MHz range and will fit in the footprint and same pinout as the 9x14mm you have. Some VCOs have larger or smaller cases but the pads may still align. 

    Disconnect C7642, R476, R3404. Then populate these three footprints with 3 resistors in a Pi attenuation network, calculate resistor values to meet RFIN signal level. (Might not be required depending on VCO Pout)

    Remove C7641. 

    Remove R91372, somehow connect RFOUT+ to the 2 pin of C7641.

    The biggest issue I see with this is that the signal integrity of RFOUT+ will be poor by running a wire over, it really needs 50Ohm line. But it might be okay to see if PLL is locked or not.

    Also, loop filter will need redesigned if you are changing VCO! Its likely that ADIsimPLL will have the VCO model, if not then just use custom VCO model in simPLL and enter kVCO and input capacitance from the VCO's datasheet. You will need a VCO with a tuning range between 0.5V and 5V since I am assuming this board has a passive loop filter.

    Regards,

    Alex