Hi,
Working on an application which has 1 PPS input from GPS and have available 24 MHz clock from OCXO. Need 1 PPS jitter clean up and need to generate 1 PPS and 10 MHz outputs with the 10 MHz signal being sync’d to the 1 PPS signal. I’ve read through the AD9544 and AD9545 datasheets and also through some of the issues posted on support community. I have the AD9544 evaluation board. I believe I have two options.
Option 1: OCXO connected as clock source to AD9544. 1 PPS connected to REFBB, single ended.
Option 2: Use onboard crystal as clock source and connect 1 PPS to REFBB and OCXO to other reference input and use system clock compensation method 3 (AD9545 datasheet).
1 PPS drift determined by OCXO drift in both cases when 1 PPS input not available.
In order to set up the eval board it looks like (from community post) the “internal zero delay setup” needs to be used but is not available in the AD9544 ACE software so need to reprogram the board as AD9545. Is this still the case?
I have option 1 setup/connected currently and have been able to get outputs, and inputs show as valid but I haven’t been able to get the DPLL to lock, only shows it as active.
Thanks in advance.
Paul
