The 10 MHz clock reference is given to input 3, and the vcxo frequency value is 50 MHz. The divider for vcxo is 5 and for input 3 is 1. But for lock the clock shall be disable PLL1 PFD DOWN and PLL1 PFD UP , that isn't true and i think that clock lock for PLL1 is fake.
To determine if the clock lock was real,clock input 1 was given a 10 MHz signal using the signal generator . We turned off the signal generator and we found that pll 1 was still locked, and this test showed that the clock lock with disable PFD DOWN and PFD UP was fake.
please help to me for solved this problem.