AD9517-3 output clock is not stable.

Hi Team,

We are using AD9517-3 part in one of our project to generate  ADC sampling clock input.

Used 10 MHz single ended  LVCMOS as reference input to clock generator, programmed  SPI registers to enable   internal PLL and VCO to obtain the 500 MHZ output frequency on OUT1 channel.With this settings we observed output frequency is not stable it is in the range of 494 MHz to 510MHz as shown below image.

With external VCO of frequency 1 GHZ,  clock generator output frequency is 500 MHz and waveform is proper.

Attached output frequency waveform captured by spectrum analyser when internal VCO used . 

Loop Filter for a PLL Using the Internal VCO values:
C1 =22pF

C2 =270pF

C3 =9pF

R1 =1.74K


Please refer the below register  setting for the internal VCO.

VCO Frequency = 2 GHz

R Divder - 1

N divider -200 =(PXB)+A =(16x12)+8

0x0000 0x18
0x0001 0x00
0x0002 0x10
0x0003 0x53
0x0004 0x00
0x0010 0x7C
0x0011 0x01
0x0012 0x00
0x0013 0x08
0x0014 0x0C
0x0015 0x00
0x0016 0x05
0x0017 0x00
0x0018 0x07
0x0019 0x49
0x001A 0x00
0x001B 0xA0
0x001C 0x02
0x001D 0x08
0x001E 0x00
0x001F 0x0E
0x00A0 0x01
0x00A1 0x00
0x00A2 0x00
0x00A3 0x01
0x00A4 0x00
0x00A5 0x00
0x00A6 0x01
0x00A7 0x00
0x00A8 0x00
0x00A9 0x01
0x00AA 0x00
0x00AB 0x00
0x00F0 0x0B
0x00F1 0x08
0x00F4 0x08
0x00F5 0x08
0x0140 0x42
0x0141 0x43
0x0142 0x42
0x0143 0x42
0x0190 0x00
0x0191 0x00
0x0192 0x00
0x0196 0x00
0x0197 0x80
0x0198 0x00
0x0199 0x00
0x019A 0x00
0x019B 0x21
0x019C 0x20
0x019D 0x00
0x019E 0x00
0x019F 0x00
0x01A0 0x11
0x01A1 0x20
0x01A2 0x00
0x01A3 0x00
0x01E0 0x00
0x01E1 0x02
0x0230 0x00
0x0231 0x00
0x0232 0x01

I have did the below experiment,

Removed on board 10 MHz oscillator and fed 10Mhz from function generator. Same issue is observed.

40mV p-p ripple is observed on 3.3V supply rail , which is input supply of Clock generator. is it ok ?

Please suggest me how to resolve this issue.



  • 0
    •  Analog Employees 
    on Jan 19, 2021 2:45 PM 1 month ago


    I took your register values and I configured an AD9516-3 evaluation board ( I do not have an AD9517-3 board, but the AD9516-3 is very similar to the AD9517-3). I provided a 10 MHz clock at REF1 connector of the board. It was not a CMOS input as the path is ac coupled. It was 400mVp-p. I calibrated the VCO and then the PLL locked

    I looked at the OUT1=500MHz with a phase noise analyzer and it seemed to me a nice output.

    Because you say that with internal VCO you have stability problems and with external VCO you do not, I have to ask you if you calibrate the internal VCO. Does the PLL lock?

    How did you chose the values of the look filter components?