Customer FPGA will get IEEE 1588 Timestamps then sync AD9542. How to sync IEEE 1588 with AD9542?
Customer have two questions.
1. Customer get IEEE 1588 Timestamps then use SPI to tuning output clock for synchronization. if they input syncE(156,25MHz) to AD9542 for reference clock and enter DPLL, it it ok for IEEE 1588 synchronization? or they need close DPLL to let AD9542 at open loop situation the use SPI tuning output clock for synchronization? Is it normal?
2. PLL1 setting to syncE,use REF A as reference input , PLL0 setting to 1588, If PLL1 use snycE for synchronization, is it possible to enter PLL0 for reference clock?