ad9542 IEEE 1588 sync

Hello

           Customer FPGA will get IEEE 1588 Timestamps  then sync AD9542. How to sync IEEE 1588 with AD9542? 

           Customer have two questions.

1. Customer get IEEE 1588 Timestamps   then use SPI to tuning output clock for synchronization. if they input syncE(156,25MHz) to AD9542 for reference clock and enter DPLL, it it ok for IEEE 1588 synchronization? or they need close DPLL to let AD9542 at open loop situation the use SPI tuning output clock for  synchronization? Is it normal? 

2. PLL1 setting to syncE,use REF A as reference input , PLL0 setting to 1588, If PLL1 use snycE for synchronization,  is it possible to enter PLL0 for reference clock?  

BR

Patrick

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  • +1
    •  Analog Employees 
    on Jan 5, 2021 9:09 PM

    Hi Patrick,

    This is not a simple issue and will probably require more interaction with your customer.  I will attempt to answer your questions and also ask for additional information for clarity.  The AD9542 can be used in many different ways.

    1) The customer will need a 1588 Servo that produces frequency adjustments in parts-per-billion (ppb) relative to the AD9542's present output frequency.  We can provide python code written in the style of C to convert the ppb adjustment to the correct SPI/I2C writes for one of the DPLL's free running tuning words (FRTW).  Programming the FRTW should include safeguards to ensure that the frequency step is not too large to cause the DPLL's subsequent APLL to come unlocked.  

    I will attach a diagram that shows one way to configure the AD9542 for SyncE and 1588 Servo's.  The process leverages the AD9542's System Clock Compensation function.  SyncE is used as an input to DPLL0.  The outputs of Ch0 will have the stability of the SyncE source.  Furthermore the SyncE stability provides System Clock Compensation to DPLL1.  DPLL1 is operated in open loop mode.  This means that the output frequency is a function of the FRTW (updated by the 1588 Servo) and the System Clock (compensated by SyncE).  Please see the System Clock Compensation section in the AD9545 datasheet.  (The AD9542 datasheet is being updated to match the AD9545 for common functions.)

    There are other ways to configure the AD9542 that depend on Holdover requirements during the loss of 1588 and/or SyncE.  It is also important to consider what the output clocks (not just the clocks feeding back to the FPGA/ASIC for the 1588 Servo) require.  Please check with your customer to determine the reference for each of the output channels.

    2) I'm not sure I understand your 2nd question.  DPLL1 can have SyncE as its reference.  DPLL0 can be controlled by the 1588 servo as mentioned above.  As I noted above, we can apply System Clock Compensation to DPLL0 based on the stability of DPLL1.  This will limit DPLL0's wander between SPI/I2C writes match the stability of SyncE.

  • +1
    •  Analog Employees 
    on Jan 5, 2021 10:09 PM in reply to ad9020
  • 0
    •  Analog Employees 
    on Jan 26, 2021 9:28 PM in reply to PChen833

    I did not see the attachment.  Please try to send it again.  I'll make the appropriate changes and explain them for your customer.

  • Thanks. But I can not upload the file directly via below insert index. So I upload file on below google link.

    Thank you. 

  • +1
    •  Analog Employees 
    on Jan 29, 2021 1:39 AM in reply to PChen833

    I haven't completed the analysis for the proper configuration, but the first thing that I noticed is a 30.72MHz System Clock input.  I mentioned the phase noise concern when using the low frequency 30.72MHz in an earlier response.  What are the phase noise requirements of the customer?  What is the source of the 30.72MHz (TCXO?).  I will attempt to provide a solution that uses a higher frequency Xtal for the System clock input and use the 30.72MHz as a Reference input for system clock compensation.  A 30.72MHz system clock will probably not give adequate phase noise for a transceiver. 

    Can the customer's system assume that SyncE will always be present or is there a mode where SyncE may be switching to a different source and holdover stability of the local 30.72MHz XO be required?

    From your earlier post, I'm surprised that the transceiver clock of DPLL0 is only traceable to SyncE and not 1588.  Is this the customer's intent?

  • Hello

                Customer could  accept 48MHz or higher frequency not must 30.72MHz(TCXO). They will depend on our setting and look forward to get complete and proper configuration for this application.  

                They use DPLL0-> PHY (SyncE) and DPLL1 -> 1588 on their configuration. They have another question as below. Could they switch 1PPS for reference not SyncE? Has any questions and how to configure for 1PPS reference? Thank you.  

      

    BR
    Patrick

  • +1
    •  Analog Employees 
    on Jan 29, 2021 1:51 PM in reply to PChen833

    At the risk of bragging, the AD9545 can support almost any input including 1PPS.  However, I need more information regarding what signals are available all the time and what signals can be interrupted and the requirements for holdover.  

    I think it best for me to contact you via email to address these very specific items.  The good news is that the AD9545 family should be able to meet your customer requirements due to its flexibility.

Reply
  • +1
    •  Analog Employees 
    on Jan 29, 2021 1:51 PM in reply to PChen833

    At the risk of bragging, the AD9545 can support almost any input including 1PPS.  However, I need more information regarding what signals are available all the time and what signals can be interrupted and the requirements for holdover.  

    I think it best for me to contact you via email to address these very specific items.  The good news is that the AD9545 family should be able to meet your customer requirements due to its flexibility.

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