ad9542 IEEE 1588 sync

Hello

           Customer FPGA will get IEEE 1588 Timestamps  then sync AD9542. How to sync IEEE 1588 with AD9542? 

           Customer have two questions.

1. Customer get IEEE 1588 Timestamps   then use SPI to tuning output clock for synchronization. if they input syncE(156,25MHz) to AD9542 for reference clock and enter DPLL, it it ok for IEEE 1588 synchronization? or they need close DPLL to let AD9542 at open loop situation the use SPI tuning output clock for  synchronization? Is it normal? 

2. PLL1 setting to syncE,use REF A as reference input , PLL0 setting to 1588, If PLL1 use snycE for synchronization,  is it possible to enter PLL0 for reference clock?  

BR

Patrick

Parents
  • +1
    •  Analog Employees 
    on Jan 5, 2021 9:09 PM 1 month ago

    Hi Patrick,

    This is not a simple issue and will probably require more interaction with your customer.  I will attempt to answer your questions and also ask for additional information for clarity.  The AD9542 can be used in many different ways.

    1) The customer will need a 1588 Servo that produces frequency adjustments in parts-per-billion (ppb) relative to the AD9542's present output frequency.  We can provide python code written in the style of C to convert the ppb adjustment to the correct SPI/I2C writes for one of the DPLL's free running tuning words (FRTW).  Programming the FRTW should include safeguards to ensure that the frequency step is not too large to cause the DPLL's subsequent APLL to come unlocked.  

    I will attach a diagram that shows one way to configure the AD9542 for SyncE and 1588 Servo's.  The process leverages the AD9542's System Clock Compensation function.  SyncE is used as an input to DPLL0.  The outputs of Ch0 will have the stability of the SyncE source.  Furthermore the SyncE stability provides System Clock Compensation to DPLL1.  DPLL1 is operated in open loop mode.  This means that the output frequency is a function of the FRTW (updated by the 1588 Servo) and the System Clock (compensated by SyncE).  Please see the System Clock Compensation section in the AD9545 datasheet.  (The AD9542 datasheet is being updated to match the AD9545 for common functions.)

    There are other ways to configure the AD9542 that depend on Holdover requirements during the loss of 1588 and/or SyncE.  It is also important to consider what the output clocks (not just the clocks feeding back to the FPGA/ASIC for the 1588 Servo) require.  Please check with your customer to determine the reference for each of the output channels.

    2) I'm not sure I understand your 2nd question.  DPLL1 can have SyncE as its reference.  DPLL0 can be controlled by the 1588 servo as mentioned above.  As I noted above, we can apply System Clock Compensation to DPLL0 based on the stability of DPLL1.  This will limit DPLL0's wander between SPI/I2C writes match the stability of SyncE.

  • +1
    •  Analog Employees 
    on Jan 5, 2021 10:09 PM 1 month ago in reply to ad9020
  • Hello

               If all output clock used for IEEE1588 related device, both DPLLs should set to open loop and controlled by PTP4L. In this condition, we cannot use any reference input (REFA/REFB) as reference clock, am I right?

               if customer will use 30.72 MHz or 12.8MHz as system clock. if these two frequency is OK?

    BR

    Patrick

  • +1
    •  Analog Employees 
    on Jan 14, 2021 2:14 PM 1 month ago in reply to patrickchen@morrihan.com

    A better configuration is to have one of the DPLL's in open loop and have the other DPLL in cascade mode.  See Cascaded DPLL Configuration section in the AD9545 DS.  This mode creates a Leader/Follower configuration where the Leader DPLL is open loop and controlled by the 1588 Servo updates to the Free Run Tuning Word.  The Follower DPLL uses the feedback of the Leader DPLL as its reference input.  This ensures that both DPLL's track.

    A SyncE (or other stable reference) can still come in on one of the Ref inputs and drive the Aux DPLL.  The Aux DPLL is used for System Clock Compensation of DPLL0/1.  

    System Clock frequencies of 30.72MHz are not recommended because the lower System Clock frequency will degrade phase noise on the outputs.  See the System Clock PLL section of the AD9545 datasheet that recommends System Clock frequencies around 50MHz.  The minimum allowed System Clock is 20MHz.  The System Clock input path needs to have a low phase noise source such as an Xtal for optimum performance.  Furthermore, in Xtal mode the System Clock frequency doubler is used.  The doubler should not be used if the input source is an XO due to concerns about a non-50% input duty cycle.  (This constraint will be noted in an upcoming rev of the AD9545 datasheet.) 

    Use the guidance from my previous response to determine if a spur location associated with a 30.72MHz clock would be a problem.  (156.25MHz - 30.72MHz x 5)

  • Hello

                  Per above description, SyncE can be used to drive the Aux DPLL. But it do not form a close loop to tracking the phase. Does it has the same performance behavior as DPLL? It is concerned by customer. Thank you. 

     

    “A SyncE (or other stable reference) can still come in on one of the Ref inputs and drive the Aux DPLL.  The Aux DPLL is used for System Clock Compensation of DPLL0/1.”

    BR

    Patrick

  • +1
    •  Analog Employees 
    on Jan 20, 2021 1:23 PM 1 month ago in reply to patrickchen@morrihan.com

    Patrick,

    As stated above, AuxDPLL is used for System Clock compensation.  The concept of System Clock compensation (SCC) needs to be understood by the customer.  SCC is used to stabilize the frequency of the Leader DPLL (assuming cascade mode) which is driven by Free Run Tuning Word (FRTW) updates  The FRTW updates (provided by the 1588 Servo) are used to lock the phase due to the feedback of a 9542 output back to the processor that is running the 1588 Servo. 

    The Leader DPLL's output is determined by the FRTW updates and the System Clock.  Without SCC, the System Clock would track the drift of the Xtal between FRTW updates.  Use of the AuxDPLL to provide SCC to the Leader DPLL allows the Leader DPLL to have the frequency stability of the AuxDPLL's input (SyncE in this case) between FRTW updates.  Remember in this example the Leader DPLL is "open loop" at the AD9542 chip level depending on FRTW updates.  However it is "closed loop" when operating as part of the 1588 Servo.

  • Hello

        Attached is  .cso file with reference clock and output clock assigned. Customer do not know how to configure the “System Clock Compensation”, could you help on it? Also, please help to review other setting in this .cso file.Thank you. 

     

    DPLL requirements as below:

    1. REF A (15.625MHz) is SyncE source from PHY and used as an input to DPLL0. Need to comply G.8262 EEC1 so I set loop bandwidth of profile 0 as 5 Hz (1 Hz < BW < 10 Hz). OUT0A/0B/0C is used by FPGA as reference clock of transceiver and other logic.
    2. DPLL1 is operated in open loop mode and controlled by 1588 servo. Need to comply G.8273.2 so loop bandwidth should be 0.05 Hz < BW < 0.1 Hz but I do not know where to set it. DPLL1  also need has SyncE stability from DPLL0. OUT1A/1B is used by 1588 related logic (ex: ToD counter)

     

    BR

    Patrick

Reply
  • Hello

        Attached is  .cso file with reference clock and output clock assigned. Customer do not know how to configure the “System Clock Compensation”, could you help on it? Also, please help to review other setting in this .cso file.Thank you. 

     

    DPLL requirements as below:

    1. REF A (15.625MHz) is SyncE source from PHY and used as an input to DPLL0. Need to comply G.8262 EEC1 so I set loop bandwidth of profile 0 as 5 Hz (1 Hz < BW < 10 Hz). OUT0A/0B/0C is used by FPGA as reference clock of transceiver and other logic.
    2. DPLL1 is operated in open loop mode and controlled by 1588 servo. Need to comply G.8273.2 so loop bandwidth should be 0.05 Hz < BW < 0.1 Hz but I do not know where to set it. DPLL1  also need has SyncE stability from DPLL0. OUT1A/1B is used by 1588 related logic (ex: ToD counter)

     

    BR

    Patrick

Children
  • 0
    •  Analog Employees 
    on Jan 26, 2021 9:28 PM 1 month ago in reply to patrickchen@morrihan.com

    I did not see the attachment.  Please try to send it again.  I'll make the appropriate changes and explain them for your customer.

  • Thanks. But I can not upload the file directly via below insert index. So I upload file on below google link.

    Thank you. 

  • +1
    •  Analog Employees 
    on Jan 29, 2021 1:39 AM 28 days ago in reply to patrickchen@morrihan.com

    I haven't completed the analysis for the proper configuration, but the first thing that I noticed is a 30.72MHz System Clock input.  I mentioned the phase noise concern when using the low frequency 30.72MHz in an earlier response.  What are the phase noise requirements of the customer?  What is the source of the 30.72MHz (TCXO?).  I will attempt to provide a solution that uses a higher frequency Xtal for the System clock input and use the 30.72MHz as a Reference input for system clock compensation.  A 30.72MHz system clock will probably not give adequate phase noise for a transceiver. 

    Can the customer's system assume that SyncE will always be present or is there a mode where SyncE may be switching to a different source and holdover stability of the local 30.72MHz XO be required?

    From your earlier post, I'm surprised that the transceiver clock of DPLL0 is only traceable to SyncE and not 1588.  Is this the customer's intent?

  • Hello

                Customer could  accept 48MHz or higher frequency not must 30.72MHz(TCXO). They will depend on our setting and look forward to get complete and proper configuration for this application.  

                They use DPLL0-> PHY (SyncE) and DPLL1 -> 1588 on their configuration. They have another question as below. Could they switch 1PPS for reference not SyncE? Has any questions and how to configure for 1PPS reference? Thank you.  

      

    BR
    Patrick

  • +1
    •  Analog Employees 
    on Jan 29, 2021 1:51 PM 27 days ago in reply to patrickchen@morrihan.com

    At the risk of bragging, the AD9545 can support almost any input including 1PPS.  However, I need more information regarding what signals are available all the time and what signals can be interrupted and the requirements for holdover.  

    I think it best for me to contact you via email to address these very specific items.  The good news is that the AD9545 family should be able to meet your customer requirements due to its flexibility.