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Basic setup to comminicate to LTC6811 or LTC6804


I am trying to communicate to an LTC6811(-2) and testwise LTC6804(-1) using an STM32F103. Tried so far two LTC6811 and one LTC6804 without any success.

What is the minimum hardware setup required? Do I need V+ to be connected or is for communication test Vreg sufficient? Can WDT, DRIVE and SWTEN be left floating for a test?

And what command can be used to test communication after power-on?

As a minimum setup I hooked up the LTC6811-2 as follows:

  • Pins 45..48: A0 .. A3 = V- (GND)   [for LTC6804-1: Pin48 to Pin47 via 100R, Pin46 shorted to Pin45 and both to V- via 20k]
  • Pin 44: SDO = STM32 MISO + via 4k7 to +3V3 (STM32 supply)
  • Pin 43: SDI = STM32 MISO
  • Pin 42: SCK = STM32 CLK
  • Pin 41: CSB = STM32 CS
  • Pin 40: ISOMD = V- (GND)
  • Pin 37: Vreg = +5V
  • Pins 30,31: V- = GND

I am measuring 1mA continuously on the 5V pin. That value does not match any value range for Vreg supply current from the data sheet, but is also not completely out of range.

In what states are Core and isoSPI module starting? If core starts in Standby I would have expected it to go to sleep after two seconds if there is no activity on the SPI.

Is that basic hardware setup OK in general to just testing communication to the device?

Software wise I try to communicate to the LTC as follows:

  • SPI Mode 3 (CPOL = 1, CPHA = 1 (2nd Edge))
  • MSB first
  • Motorola 8Bits
  • tried 125kBit/s and 500kBit/s

For testing I programmed every 10 seconds to read three times the config with a second in between

  • # Wakeup
  • cs low for 1ms
  • wait 1ms
  • cs high for 1ms
  • # Write command
  • cs low
  • send [0x00, 0x02, 0x2b, 0x0A]
  • (cs high)
  • # Read data
  • (cs low)
  • read  8Bytes (send 0xFF for reading)
  • cs high

Double checked the activity on the SPI lines/pins via oscilloscope, CS, CLK and SDI looks fine from my view, but SDO line stays pulled to 3V3, no reaction from the LTC(s) whatoever.

What am I doing wrong?

How can I get started on the devices or a simple test if they are OK after all?

Thanks for your support.

  • V+ should be at least 11V to ensure all the workings of the parts are powered. Drive and WDT can be left open, though a digital input like SWTEN should be committed to a logic level. The commands and data should all be transferred while CS is low or there is no activity by the IC. Additionally, the IC will require a correct PEC in order to respond (or the command is rejected), and must be awakened beforehand with some CS toggles (I think you may have done that, you can tell if drive goes on [~5.6V]). Given the complexity involved, it's a good idea to use the demo boards and GUI we have for these ICs (same s/w for each) so that there is a working example to work from. The GUI will also show the byte formation for a particular command including the PEC, so this can be useful in hard-coding some PECs during initial operation.

  • Hi,

    I'm testing the LTC6811 in isoSPI mode along with LTC6820 with an STM32F3, and when I provide around 36V on V+, the drive voltage goes to ~5.6V and then turns off in few seconds. I'm assuming for the drive voltage to be on, the core module should be on and that only happens when the CS pin on LTC6820 is toggled few times? Please confirm this.

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  • The DRIVE pin will go low after WDT expires and it is not particularly dependent on CS pin toggling. If there is a valid communication in the SPI lines the drive will stay at 5.7V. Please see CORE LTC6811 STATE DESCRIPTIONS on page20 of the datasheet it will give you more information on the all the state of operation of the IC

  • Thank you for your help!

    I've gone through the State descriptions given and the LTC6811 is coming out of sleep mode, with the drive voltage around 5.7V. I'm using the npn pass regulator circuit to provide VREG with 5V. I'm using two LTC6811-1 in the stack with daisy chain configuration.However the current consumption of the VREG pin is extremely high, with both the VREGs together consuming around 150mA of current. There are no shorts or any other obvious issues, i'm attaching my schematic, please let me know possible reasons!


  • I believe this similar issue has been described in another forum?    LTC6811 High VREG current consumption  

    150mA is actually a lot of current. How are you measuring it? Are you only measuring the current which is going inside the IC? because I can see that there is a blue LED connected to VREG which is not recommended in our design. we usually connect the LED indicator before the collector of NPN. So it will operate only when drive goes to 5.7V. 

    In your current measurement, does it also have the current due to the LED? 

    Secondly the major problem I can see that in your schematic you have only used 1 NPN to power up 2 BMS ICs. This will not work because you have lost your isolation and it is very risky to operate in this manner. So the VREG voltage that is being generated is with reference to VSS and not GND5 and hence you might see the IC not function properly.  

    I will advise you to make this change as soon as possible and not do any further testing with this configuration. 

  • Hi, 

    Yes I'm measuring only the current going to the ICs, as I'm using a DC power supply ( which indicates the supply current) to power both the LTC6811. The current measurement does not include the LED current as I've disconnected the LED in my setup and checked the current consumption.

    Please check again, I've used two npn transistors, one for each ltc6811 as given in the schematic.

    GND5( gnd of the top ltc6811 in the stack) is at the same potential as the 12th cell of the bottom stack, that is fine right?

    Please let me know if there are any other possible issues or solutions 

  • Apologies, I did not check the 2nd NPN for VREG_1 connection. Your circuit looks fine to me. GND5 and CELL12/6.2B can be at the same potential. However the high VREG current doesn't look correct to me. To debug this I need some more information. 

    I'm using a DC power supply ( which indicates the supply current) to power both the LTC6811

    How is the DC power supply connected? Can you please tell me at which 2 nets in the schematic are you connecting the DC supply+ and DC supply- ? As per your statement i understood that it supplies both the ICs does it supply V+ to the IC or VREG?

    Is it connected to VREG pin of the IC or is it only connected to V+ of top IC and V- of bottom IC? 

    How are you simulating cell voltages? are you using resistor divider circuit or are you connecting actual cells for C1 to C20? 

  • I'm using a 60V DC supply. The DC supply + is connected to the V+ of the top ltc6811 (through the RC circuit from CELL24) and the DC supply- is connected to VSS (ground of bottom ltc6811)

    I'm using a resistor divider circuit to simulate the cell voltages, and hence I'm providing 36V to V+ of the bottom IC and providing 24V to the V+ of the top IC(referenced to CELL12/GND5). In this manner I'm simulating 20 cells.

    I've also checked by powering on only the bottom ltc6811, by providing 48V to CELL12 and VSS, and even then the current consumption of the IC was around 150mA.

    Do note, I'm not considering the current consumption of the resistor divider circuit in this.

    Your inputs are appreciated, do let me know your thoughts regarding this, thanks!

  • Alright this makes sense, so its not just the VREG which is drawing 150mA but the entire system. This again is still too much. So to further debug can you check the voltage drop across R270 and R269? Also, what is the VREG voltage you see at the emitter of the NPN? 

    R270 is in the collector path which will help us identify current flowing through VREG. As per electrical characteristic of the IC this current should not be more than 12.3mA. So the current that you see at the collector must be much lesser than this. So the voltage drop you must see should be around ~1V and not more than that. 

    Likewise for R269, the current going in should not be more than 0.775mA (in measure state) so the voltage drop expected here should be <77.5mV

    Similarly the same exercise can be repeated for bottom IC by checking voltage drop across R57, R56 and measuring VREG voltage when there is a valid SPI communication.

    If these voltages are in range then the IC is getting the correct supply voltage and current. 

  • Hi,

    I've checked by sending valid SPI communication, and the voltage drop across R270 and R57 is 13.20V. The voltage drop across R269 is 0.043V( 43mV) and R56 is 0.018V (18mV). VREG for both of them is 5.05V. Clearly the voltage drop across R270 and R57 is extremely high and therefore the current consumption as well. Please let me know how i can debug this issue.

    I also have another query. I'm testing one LTC6813 as well, with the same test setup of 60V dc supply and resitor divider circuit to simulate the voltages, and i'm facing a different issue. Initially i'd tested it and I was able to read the cell voltages by sending the ADCV command and everything was working fine, with VDRIVE = 5.7V and VREG = 5V and current consumption around 10mA.  However, now I am not able to do so. The drive voltage is now 4.6V and VREG = 3.9V. The schematic is similar to the one I've shared, and I've checked the voltage drops for the RC filter circuits going to V+ as well as the RC filter circuit going to the collector of the NPN. The voltage drop across the 100E resistor going to V+ is 0.44V( 440mV) and the drop across the 100E resistor going to the collector of the NPN is 56V. This is extremely strange, as it was working before.

    Please provide suggestions to debug both these issues.

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  • Hi   

    I've responded to your inputs, please let me know soon regarding this and how to go about debugging this issue. 

  • This indeed is a strange behavior. But since IC is generating 5.7V DRIVE and you are getting 5V VREG voltage. I still hardly doubt that the IC is damaged. 

    1. Are you seeing this behavior in 1 board or all boards? Did you check it in a different board? 
    2. Have you already checked that IC is communicating properly? If not can you send WRCFGA with REFON bit set and read the same bit back again from RDCFGA. If this passes then it means IC is working fine and this high current is going somewhere else. 

    Are there any physical soldering issues on board? Can you verify the same physically in the path of the NPN where VREG is generated?

    Can you share your layout file for review? If you are not comfortable sharing the layout files here you can send it on