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HMC7043 : could not turn the "Clock outputs phases status" to 1 in SYSREF generation


I have a question about HMC7043 from our customer.
He has a trouble of SYSREF output.
He could generate one pulse SYSREF but "clock outputs phases status bit" is fixed to 0.

The input/output condition is followings.

  CLOCK : 2GHz

  ADC SAMPLE CLOCK (AD0CLK, AD1CLK)            : 2GHz
  * pulse generator mode and generate one pulse SYSREF

  The customer was refferrd the datasheet p.23 "TYPICAL PROGRAMMING SEQUENCE".
  Please see atatched file.

  In this sequence, in the 10th, it confirm the "clock outputs phases status bit" turn to  1.
  But the readback value of 0x007D = 0x00.
  It means "Sync request status" = 0 , "Clock outputs phases status" = 0 , "SYSREF sync status" = 0 and reserved bit0 = 0.
  And he checked the "Clock outputs phase status" via GPO pin, it output level high.
  These two indications(status) are not match.
  And he confirmed that the SYSREF is output and it synchronize to CLOCK.

I would like to have your advice to solve the problem and to turn the status to 1 for "Clock outputs phases status".
Please point us if the startup sequence has mistake.

Best regards.


(1) Power-Up and H/W reset
(2) CLKIN Input Buffer Control
[Write] Address=0x000A, Data=0x01 (Enable internal 100 �� termination) 
(3) Bias Setting
[Write] Address=0x009F, Data=0x4D (Low Power Setting) 
[Write] Address=0x00A0, Data=0xDF (High Power Setting)
(4) SYSREF Timer
[Write] Address=0x005C, Data=0x00 (Timer[7:0]=0x00 0.78125MHz)
[Write] Address=0x005D, Data=0x0A (Timer[11:8]=0x0A 0.78125MHz)
(5) Pulse Generator Mode Selection
[Write] Address=0x005A, Data=0x01 (1 pulse)
(6) CH1-Ch13 Driver settings
[Write] Address=0x00D0, Data=0x10 (FPGA_REFCLK0: LVDS) 
[Write] Address=0x00DA, Data=0x10 (FPGA_REFCLK1: LVDS) 
[Write] Address=0x010C, Data=0xB0 (AD1_SYSREF: Dynamic, LVDS) 
[Write] Address=0x0116, Data=0x08 (AD1_CLK: LVPECL) 
[Write] Address=0x0120, Data=0x08 (AD0_CLK: LVPECL) 
[Write] Address=0x0134, Data=0xB0 (AD0_SYSREF: Dynamic, LVDS) 
[Write] Address=0x013E, Data=0xB0 (FPGA_SYSREF: Dynamic, LVDS)
[Write] Address=0x0148, Data=0x10 (FPGA_GLBLCLK0: LVDS) 
[Write] Address=0x0152, Data=0x10 (FPGA_GLBLCLK1: LVDS)

## settings for not use port
[Write] Address=0x00E4, Data=0x01
[Write] Address=0x00EE, Data=0x01
[Write] Address=0x00F8, Data=0x01
[Write] Address=0x0102, Data=0x01
[Write] Address=0x012A, Data=0x01
(7) CH1-Ch13 divider settings
[Write] Address=0x00C9, Data=0x14 (FPGA_REFCLK0[LSB]: 100MHz)
[Write] Address=0x00CA, Data=0x00 (FPGA_REFCLK0[MSB]: 100MHz)
[Write] Address=0x00D3, Data=0x14 (FPGA_REFCLK0[LSB]: 100MHz)
[Write] Address=0x00D4, Data=0x00 (FPGA_REFCLK0[MSB]: 100MHz)
[Write] Address=0x0105, Data=0x00 (AD1_SYSREF[LSB]: 0.78125MHz) 
[Write] Address=0x0106, Data=0x0A (AD1_SYSREF[MSB]: 0.78125MHz)
[Write] Address=0x010F, Data=0x01 (AD1_CLK[LSB]: 2GHz) 
[Write] Address=0x0110, Data=0x00 (AD1_CLK[MSB]: 2GHz) 
[Write] Address=0x0119, Data=0x01 (AD0_CLK[LSB]: 2GHz) 
[Write] Address=0x011A, Data=0x00 (AD0_CLK[MSB]: 2GHz) 
[Write] Address=0x012D, Data=0x00 (AD0_SYSREF[LSB]: 0.78125MHz) 
[Write] Address=0x012E, Data=0x0A (AD0_SYSREF[MSB]: 0.78125MHz)
[Write] Address=0x0137, Data=0x00 (FPGA_SYSREF[LSB]: 0.78125MHz) 
[Write] Address=0x0138, Data=0x0A (FPGA_SYSREF[MSB]: 0.78125MHz)
[Write] Address=0x0141, Data=0x28 (FPGA_GLBLCLK0[LSB]: 50MHz) 
[Write] Address=0x0142, Data=0x00 (FPGA_GLBLCLK0[MSB]: 50MHz)
[Write] Address=0x014B, Data=0x28 (FPGA_GLBLCLK1[LSB]: 50MHz) 
[Write] Address=0x014C, Data=0x00 (FPGA_GLBLCLK1[MSB]: 50MHz)

## settings for not use port
[Write] Address=0x00DD, Data=0x14
[Write] Address=0x00DE, Data=0x00
[Write] Address=0x00E7, Data=0x14
[Write] Address=0x00E8, Data=0x00
[Write] Address=0x00F1, Data=0x14
[Write] Address=0x00F2, Data=0x00
[Write] Address=0x00FB, Data=0x14
[Write] Address=0x00FC, Data=0x00
[Write] Address=0x0123, Data=0x14
[Write] Address=0x0124, Data=0x00
(8) Channel Enabe / Disable settings
[Write] Address=0x00C8, Data=0xD1 (ch0 FPGA_REFCLK0: Disable) 
[Write] Address=0x00D2, Data=0xD1 (ch1 FPGA_REFCLK1: Disable)
[Write] Address=0x00DC, Data=0xD0 (ch2 do not use: Disable) 
[Write] Address=0x00E6, Data=0xD0 (ch3 do not use: Disable) 
[Write] Address=0x00F0, Data=0xD0 (ch4 do not use: Disable) 
[Write] Address=0x00FA, Data=0xD0 (ch5 do not use: Disable) 
[Write] Address=0x0104, Data=0xDD (ch6 AD1_SYSREF: Disable) 
[Write] Address=0x010E, Data=0xD1 (ch7 AD1_CLK: Disable) 
[Write] Address=0x0118, Data=0xD1 (ch8 AD0_CLK: Disable) 
[Write] Address=0x0122, Data=0xD0 (ch9 do not use: Disable)
[Write] Address=0x012C, Data=0xDD (ch10 AD0_SYSREF: Disable)
[Write] Address=0x0136, Data=0xDD (ch11 FPGA_SYSREF: Disable)
[Write] Address=0x0140, Data=0xD1 (ch12 FPGA_GLBLCLK0: Disable) 
[Write] Address=0x014A, Data=0xD1 (ch13 FPGA_GLBLCLK1: Disable)
(9) Restart dividers/FSMs
[Write] Address=0x0001, Data=0x02 (Restart divider/FSMs = 1) 
[Write] Address=0x0001, Data=0x00 (Restart divider/FSMs = 0) 
[Write] Address=0x0001, Data=0x80 (Reseed request = 1)
(10) Confirm the "Clock output phase status" bit
[Read] Address=0x007D Value=
  sync request status =1 (Unsynchronized)
  Clock output phase status = 0
  SYSREF sync status = 0