I have a AD9524/PCBZ(REV C), and PC is win10 64-bit.
The software is the newest version on the website(v2.1.3).
The AD9524 architecture is like this
I got good connection with the EVB including reading and writing the registers, so I suspect that the software is not the problem.
I check to see if PLL1 is working well by observing the output of PLL1_OUT, and the bit that indicates PLL1’s locking status.
Due to the VCO on the board is 122.88MHz. So I generated the same frequency cosine wave(122.88MHz, 10dBm=707.1mV) and inserted it to REFA.
Then I check the status, it said REF A receiver successfully received the signal and the VCXO did, too.
The PLL1_OUT showed nothing when VCXO output driver is off, and showed the harmonics when VCXO output driver is on.
Is there anyone could tell me the probable cause that makes the PLL1 failed to lock.