ADCLK948BCPZ Phase noise at 20 to 100MHz range

Hi,

 I am planning to use ADCLK948BCPZ part for clock fan-out to FPGA and RF transceiver of ADRV9002 part with input clock source will be OCXO 10 to 100MHz range.


For ADCLK948BCPZ part, the phase noise details are given for 1Ghz range in the datasheet and phase noise difference in b/w clock source (500-06672) and fanout buffer with multiplier like below,
~1dB @ 100KHz
~2dB @ 1MHz
~3dB @ 1MHz
~6dB @ 10Mhz


1. In my case there is no multiplier in b/w the OCXO and fanout buffer. Can u provide the phase noise difference  in the range of 10 to 100MHz input clock range for fanout buffer and consider the input phase noise details as per in the datasheet (500-06672)?


2. Please provide the clock fanout buffer phase noise details w.r.t given 10MHz clock input OCXO phase noise  as per below,


OCXO phase noise (input)               ADCLK948BCPZ phase noise
    -105dBc @ 1Hz
    -135dBc @ 10Hz
    -157dBc @ 100Hz
    -167dBc @ 1000Hz    
    -172dBc @ 10KHz
    -173dBc @ 100KHz

3. Pls suggest better phase noise clock fanout part compared to ADCLK948BCPZ fanout for my design.

Regards

James A

  • 0
    •  Analog Employees 
    on Oct 29, 2020 3:24 PM 26 days ago

    HI,

    It's not clear to me what you are asking. The figure 11 in the data sheet shows the phase noise introduced by the ADCLK948 when a 1GHZ clock created from a Wenzel 100MHz oscillator (considered to have the cleanest possible phase noise profile) multiplied by 10 is applied at the input.

    You are asking me to provide the phase noise introduced by the ADCLK948 when a 10MHz OCXO of the profile you list is applied.  I do not have that OCXO. I suggest you procure an ADCLK948 evaluation board (https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-ADCLK948.html#eb-overview) and then do the measurement.

    If you are concerned about the phase noise introduced by a  buffer, take a look at the AD9528. You can provide the OCXO clock at the VCXO_IN pins and use the chip as a buffer (see table 14, page 12, rev E data sheet for additive jitter in buffer mode). Or you can use a VCXO and generate all the clocks you need using the PLL2 of the IC using the VCXO as reference. The outputs will then be guaranteed to have the characteristics of the AD9528 PLL2 VCO, which we tested with ADRV9026 and worked very well

    Petre