Jitter values of AD9545 LVDS Output

Query 1:  See the jitter described in Table 30 of the AD9545 RevB datasheet for jitter measurements in similar configurations.  You can also view figures 3 - 10.  Typically jitter from Channel 0 will be 215-220fs.  Channel 1's jitter is slightly higher.  We would recommend using Ch0 to drive the AD9528 if possible.

Query 2: See the slew rate graphs in figures 18 and 19 of the datasheet.  We suggest using the 15mA setting to get maximum slew for the AD9528.  Given a well terminated signal path, there should be no problem meeting the 0.5v/ns.

Thanks for the quick response.

I want to know the total jitter due to AD9545 and AD9528.

Total Jitter = sqroot ((Jitter_AD9545)^2 + (Jitter_AD9528)^2);

Based on previous conversation, if we use DPLL0 then Jitter_AD9545 = 220fs

Query 1: What value should be taken as jitter of AD9528?

AD9528 will be used as buffer and from datasheet in table 14,additive jitter = 189fs

But these measurements are done considering the fact that 122.88 MHz is generated from VCXO,

how do we map to our design where 122.88MHz is generated from AD9545?                                   

Actually main intention is to know the jitter of sampling clock at the input of integrated ADC(ADRV9008-1) used in our design.

Referring to Analog Devices manual MT-008,SNR = -20log(2*pi*F*JITTER)

Correct me if i am wrong here:
                                  F in above eqn:75 MHz to 6 GHz or is it wrong?
                                  SNR:23 dB(calculated using ADI SIM RF for our configuration)
                                  BW:100 MHz

 Should Jitter obtained from the above equation be less than Total Jitter(sqroot ((Jitter_AD9545)^2  + (Jitter_AD9528)^2) for good performance in terms of jitter. 

Thanks

You are correct that one could RSS the jitter values for both the AD9545 and AD9528 to get the total expected jitter.  The equation that you reference would shows the SNR limitation due to jitter for a given frequency is also correct.  However, I don't think either will give you the answer that you seek.

The ADRV9008-1 has an on-board PLL that will partially filter reference input noise.  While a generic statement that one needs to provide a "low jitter reference" is accurate.  It isn't as important as providing a reference with a phase noise mask that mates well with the 9008-1's onboard PLL. 

With this in mind, the AD9528 is used on evaluation boards with many of the wideband transceivers.  If used in buffer mode, there is essentially no signal degradation using the AD9528 in the signal path.  Any signal degradation will come from the source driving the AD9528.  Using this information, we can conclude that the AD9545 will dominate any noise performance degradation when driving the 9008-1.  This is also supported when we take the AD9545's 220fs and RSS it with the AD9528's 112fs (12k to 20MHz; HSTL mode) to get a combined 247fs which is dominated by the AD9545.  Are  you using the AD9528 for fanout?  The AD9545 can provide both DevClk and SysRef functionality albeit with fewer output drivers.

A Wenzel oscillator is used as the "ideal" source for a Ref Clk in our characterization.  We have EVM measurements showing the performance of the AD9545 vs a Wenzel oscillator driving a similar receiver to the 9008-1.    The actual RF PLL Freq isn't as important as the RF PLL Bandwidth.  At 2.6GHz, with a 500kHz bandwidth, the receiver's 64QAM EVM is -44.8dB for the AD9545 vs. -47dB for the Wenzel.  However at 3.8GHz with a 75kHz bandwidth, the EVM is essentially the same at -39dB for both the  AD9545 and Wenzel.  Your application will need to dictate if this performance is adequate.  If not, we can provide solutions to improve the phase noise performance after the AD9545 with another jitter cleaner.

I would not recommend using LVDS mode unless you are willing to make the jitter trade-off to conserve power.  The higher swing signals reduce the jitter degradation due to slow moving LVDS signals.  LVDS would also be more sensitive to PC board transmission line mismatches.

Thanks for the detailed response.

Actually we will be using AD9528 for fanout, as no of outputs of AD9545 is not sufficient for our design requirement.

You have suggested to avoid using LVDS mode. We want to know whether this recommendation is with reference to outputs of AD9545 or AD9528 or both. Please suggest exactly which mode can be used for better jitter performance ,so that we will update the same in our design.

Thanks

Higher swing outputs typically give lower noise floor performance.  This is related to how fast the signal actually transitions through the successive input receiver's threshold.  See table 14 in the AD9528 datasheet.  Therefore 15mA settings on the AD9545 and HSTL settings on the AD9528 will give the best performance and best noise immunity from noise transients on the pcb.

Hi AD9020,

 Thanks so much for bringing out more clarity with every doubt, which motivates us to dig in to more depth and incorporate the same in our design. 

 As per your suggestion, we are planning to output AC coupled HSTL clock from AD9528 for ADC, DAC(ADRV9008-1 and ADRV9008-2) and SoC in our design.

From Table 8 of AD9528 Rev E. datasheet, Differential output voltage swing(peak value) in HSTL mode is 900-1100 mV.  Also from Fig.5, differential peak to peak voltage swing of more than 2000mV  is observed.

Now our doubt is with respect to compatibility of voltage level of HSTL clock output  with ADRV9008-1/2 and SoC used. Is there anyway to control the output swing of HSTL AC coupled output?(May be by programming it for different current settings).

From ADRV9008-1/2 datasheet,

Max peak to peak value supported is 2Vp-p but from Fig.5 of AD9528 datasheet, differential peak to peak value exceeds 2Vp-p. Please confirm if AD9528 clock outputs(AC coupled differential HSTL) can be directly interfaced to ADC,DAC in our design.

Hi AD9020,

 Thanks so much for bringing out more clarity with every doubt, which motivates us to dig in to more depth and incorporate the same in our design. 

 As per your suggestion, we are planning to output AC coupled HSTL clock from AD9528 for ADC, DAC(ADRV9008-1 and ADRV9008-2) and SoC in our design.

From Table 8 of AD9528 Rev E. datasheet, Differential output voltage swing(peak value) in HSTL mode is 900-1100 mV.  Also from Fig.5, differential peak to peak voltage swing of more than 2000mV  is observed.

Now our doubt is with respect to compatibility of voltage level of HSTL clock output  with ADRV9008-1/2 and SoC used. Is there anyway to control the output swing of HSTL AC coupled output?(May be by programming it for different current settings).

From ADRV9008-1/2 datasheet,

Max peak to peak value supported is 2Vp-p but from Fig.5 of AD9528 datasheet, differential peak to peak value exceeds 2Vp-p. Please confirm if AD9528 clock outputs(AC coupled differential HSTL) can be directly interfaced to ADC,DAC in our design.

HI,

I understand your concern. Try using the LVDS boost mode which the AD9528 data sheet says it creates a 450mV peak voltage, so a 900mVp-p differential voltage across a 100ohm resistor. See also figure 6. This also brings the differential voltage lower than 1Vp-p, the voltage indicated in the ADRV9008 table you showed.

Petre