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Jitter values of AD9545 LVDS Output


We are  referring to AD9545 evaluation  board as the reference design.

In our design ,1 PPS(single ended) from GPS will be fed to REFBB.

On board 10 MHz TCXO is being fed as REFA with following features:

Freq stability over temperature: +/- 0.1 ppm

RMS Phase Jitter(random):0.48 ps

Crystal Oscillator: same as in AD9545 evaluation board 

We will be compensating the system clock using compensation method 3 as mentioned in datasheet of AD9545.

We will be taking 2 LVDS outputs (similar to evaluation board reference): 1 PPS from OUT1A_P and OUT1A_N and

                                                                                                                 122.88 MHz from OUT1B_P and OUT1B_N

122.88 MHz differential will be given to VCXO_IN pin of AD9528(PLL1 bypassed).

AD9528 acts as a buffer and provides the sampling clock  to DAC and ADC used in our design.

Query 1: What is the jitter of 122.88MHz signal from AD9545 output?

Query 2: What will the slew rate of AD9545 output i.e.122.88 MHz output or how do i calculate(plz let me know how to calculate)

As from Fig.19,page 21 of AD9528 datasheet, it is clear that RMS phase jitter is very much degraded for slew rate less than 0.25V/ns. Also minimum value of slew rate for better performance in terms of jitter is 0.5v/ns as mentioned in datasheet.

 I want to know whether the AD9545 output clock is satisfying the min slew rate requirement of AD9528 for better performance in terms of jitter.


  • Query 1:  See the jitter described in Table 30 of the AD9545 RevB datasheet for jitter measurements in similar configurations.  You can also view figures 3 - 10.  Typically jitter from Channel 0 will be 215-220fs.  Channel 1's jitter is slightly higher.  We would recommend using Ch0 to drive the AD9528 if possible.

    Query 2: See the slew rate graphs in figures 18 and 19 of the datasheet.  We suggest using the 15mA setting to get maximum slew for the AD9528.  Given a well terminated signal path, there should be no problem meeting the 0.5v/ns.

  • Thanks for the quick response.

    I want to know the total jitter due to AD9545 and AD9528.

    Total Jitter = sqroot ((Jitter_AD9545)^2 + (Jitter_AD9528)^2);

    Based on previous conversation, if we use DPLL0 then Jitter_AD9545 = 220fs

    Query 1: What value should be taken as jitter of AD9528?

    AD9528 will be used as buffer and from datasheet in table 14,additive jitter = 189fs

    But these measurements are done considering the fact that 122.88 MHz is generated from VCXO,

    how do we map to our design where 122.88MHz is generated from AD9545?                                   

    Actually main intention is to know the jitter of sampling clock at the input of integrated ADC(ADRV9008-1) used in our design.

    Referring to Analog Devices manual MT-008,SNR = -20log(2*pi*F*JITTER)

    Correct me if i am wrong here:
                                      F in above eqn:75 MHz to 6 GHz or is it wrong?
                                      SNR:23 dB(calculated using ADI SIM RF for our configuration)
                                      BW:100 MHz

     Should Jitter obtained from the above equation be less than Total Jitter(sqroot ((Jitter_AD9545)^2  + (Jitter_AD9528)^2) for good performance in terms of jitter. 







  • You are correct that one could RSS the jitter values for both the AD9545 and AD9528 to get the total expected jitter.  The equation that you reference would shows the SNR limitation due to jitter for a given frequency is also correct.  However, I don't think either will give you the answer that you seek.

    The ADRV9008-1 has an on-board PLL that will partially filter reference input noise.  While a generic statement that one needs to provide a "low jitter reference" is accurate.  It isn't as important as providing a reference with a phase noise mask that mates well with the 9008-1's onboard PLL. 

    With this in mind, the AD9528 is used on evaluation boards with many of the wideband transceivers.  If used in buffer mode, there is essentially no signal degradation using the AD9528 in the signal path.  Any signal degradation will come from the source driving the AD9528.  Using this information, we can conclude that the AD9545 will dominate any noise performance degradation when driving the 9008-1.  This is also supported when we take the AD9545's 220fs and RSS it with the AD9528's 112fs (12k to 20MHz; HSTL mode) to get a combined 247fs which is dominated by the AD9545.  Are  you using the AD9528 for fanout?  The AD9545 can provide both DevClk and SysRef functionality albeit with fewer output drivers.

    A Wenzel oscillator is used as the "ideal" source for a Ref Clk in our characterization.  We have EVM measurements showing the performance of the AD9545 vs a Wenzel oscillator driving a similar receiver to the 9008-1.    The actual RF PLL Freq isn't as important as the RF PLL Bandwidth.  At 2.6GHz, with a 500kHz bandwidth, the receiver's 64QAM EVM is -44.8dB for the AD9545 vs. -47dB for the Wenzel.  However at 3.8GHz with a 75kHz bandwidth, the EVM is essentially the same at -39dB for both the  AD9545 and Wenzel.  Your application will need to dictate if this performance is adequate.  If not, we can provide solutions to improve the phase noise performance after the AD9545 with another jitter cleaner.

    I would not recommend using LVDS mode unless you are willing to make the jitter trade-off to conserve power.  The higher swing signals reduce the jitter degradation due to slow moving LVDS signals.  LVDS would also be more sensitive to PC board transmission line mismatches.

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