We are referring to AD9545 evaluation board as the reference design.
In our design ,1 PPS(single ended) from GPS will be fed to REFBB.
On board 10 MHz TCXO is being fed as REFA with following features:
Freq stability over temperature: +/- 0.1 ppm
RMS Phase Jitter(random):0.48 ps
Crystal Oscillator: same as in AD9545 evaluation board
We will be compensating the system clock using compensation method 3 as mentioned in datasheet of AD9545.
We will be taking 2 LVDS outputs (similar to evaluation board reference): 1 PPS from OUT1A_P and OUT1A_N and
122.88 MHz from OUT1B_P and OUT1B_N
122.88 MHz differential will be given to VCXO_IN pin of AD9528(PLL1 bypassed).
AD9528 acts as a buffer and provides the sampling clock to DAC and ADC used in our design.
Query 1: What is the jitter of 122.88MHz signal from AD9545 output?
Query 2: What will the slew rate of AD9545 output i.e.122.88 MHz output or how do i calculate(plz let me know how to calculate)
As from Fig.19,page 21 of AD9528 datasheet, it is clear that RMS phase jitter is very much degraded for slew rate less than 0.25V/ns. Also minimum value of slew rate for better performance in terms of jitter is 0.5v/ns as mentioned in datasheet.
I want to know whether the AD9545 output clock is satisfying the min slew rate requirement of AD9528 for better performance in terms of jitter.