Synchronising Two AD9528s

Hi,

I need to connect multiple ADRV9026s and a BBU such that I will exceed the 14 outputs of the AD9528 for my DEV CLK and SYSREFs.

I have seen on the AD9528 datasheet and on some threads in EngineerZone that a second AD9528 can be used as a buffer or slave to a primary AD9528, but have not seen anything outlining the optimal way to connect the second AD9528 to maximise phase noise performance while maintaining synchronisation.

I am thinking to use the first AD9528 to generate all the DEV CLK lines and one SYSREF signal which is then buffered by the second AD9528 to provide the SYSREF signals to all devices.

Is this the recommended method to connect the two AD9528s, or is there a better way? I assume buffering the DEV CLK lines will result in additive jitter and thus should be avoided if possible.

  • 0
    •  Analog Employees 
    on Oct 14, 2020 8:32 PM 1 month ago

    HI,

    it is better to bring to a transceiver both DEVCLK and SYSREF together, in pairs, because the noise profile of both is similar.

    So I propose this scheme:

    - 1st AD9528: generates 7 pairs DEVCLK+SYSREF. One pair goes to the 2nd AD9528

    - 2nd AD9528: receives DEVCLK at VCXO_IN pins and SYSREF and SYSREF_IN pins. Get DEVCLK+SYSREF outputs in pairs, both in buffer mode. Bring the VCXO_IN clock through the dividers of the distribution block, so if you need to adjust the phase alignment between the DEVCLK and SYSREF, and the delays through the AD9528, you can use the coarse/fine delay blocks.. If you need more outputs, take one DEVCLK+SYSREF pair and bring it to the 3rd AD9528

    - 3rd AD9528: proceed like the 2nd AD9528 and use the approach for how many AD9528s you need.

    Do the following procedure to obtain these outputs phase aligned:

    • Wait until PLL1 and PLL2 of 1st AD9528 are locked (register 0x0505 Status Monitor 0 Control shows this)
    • Set bit 0 (SYNC outputs) of register 0x032A to 1 in all AD9528s.
    • Clear bit 0 (SYNC outputs) of register 0x032A to all AD9528s with the exception of the 1st AD9528. This enables and aligns all their outputs, but there is nothing yet at their outputs because the 1st AD9528 did not generate yet any output.
    • Clear bit 0 (SYNC outputs) of register 0x032A to 0 in the 1st  AD9528. This enables and aligns the 1st AD9528 outputs that then flow through the other AD9528s.
    • All the AD9528s produce clocks that are synchronized to each other

    Regarding the phase noise of the outputs. The 1st AD9528 phase noise of the outputs can be found in the data sheet (Typical Performance Characteristics plots, spec tables 11 and 12). The AD9528 phase noise in buffer mode can be found in the table 14.

    We tested the AD9528 with the ADRV9026 using the 122.88MHz VCXO from Crystek CVHD-950-122.880 that it is mounted on the AD9528 evaluation board. The conclusion was that the AD9528 can be used to provide DEVCLK to ADRV9026

    Petre

  • Hi Petre.

    Thanks for the information. We will review and let you know if we have further questions.

    Brian