Is it "safe" to forward only ONE SYSREF to FPGA for Tx, Rx and ORx in JESD204B?

Hello all,

I want to reduce SYSREF lines from HMC7044 to FPGA to simplify hardware design.

In the current version, ADI uses 2 SYSREFs (one for Tx and ORx links; one for Rx link). As my understand, your motivation to do that is to perform TX | ORX and RX configuration separately and flexibly.

In my case, I have kind of fixed configuration for TX, RX, ORx; so is it safe to use only ONE SYSREF for three?

Does it have any specific constraint to do so?


Trung Nguyen