Hello,I have a question about SOURCE PROFILE register of AD9542.The SOURCE PROFILE 0 to 3 are settings for reference input each.I could understand how to use these.The SOURCE PROFILE 4 and 5 are settings for NCOx , and SOURCE PROFILE 5 and 6 are settings for DPLLx.They has same parameters as SOURCE PROFILE 0~3.I can not understand why these registers has same parameters as SOURCE PROFILE 0~3.What purpose of these registers ?How to use these SOURCE PROFILE 4~6 registers ?Best regards,y-suzuki
first I want to point out that the AD9542 and the AD9544 do not have auxiliary NCOs and auxiliary TDCs. The AD9543 and AD9545 have them.
The source profiles refer to the DPLL sources. Please do not…
The source profiles refer to the DPLL sources. Please do not confound them with the DPLL translation profiles.
The source profiles configure the way a particular reference clock, be it REFA,AA,B,BB or aux NCO0, 1 or DPLL0, DPLL1 feedback clock interacts with the DPLL when selected by the DPLL as the source of a translation profile.
Yes, every source profile has the same parameters because as a reference clock to the DPLL, the DPLL uses these parameters to characterize the lock status, reference switching behavior and the eventual offset skew it has to introduce..
The source profile 0 to 3 registers refer to the case when REFA, REFAA, REFB or REFBB are used as reference clocks for a DPLL.
The source profile 4 and 5 registers refer to the case when auxiliary NCO0 or auxiliary NCO1 are used as reference clocks for a DPLL.
The source profiles 6 and 7 registers refer to the case when the DPLLs are in cascade and the feedback clock of one DPLL is used as the reference to the other DPLL, like in the picture below taken from figure 86, page 110 of rev B AD9545 data sheet: I'm sorry, for some reason, I cannot attach a photo. Look at the configuration at the right side of that figure.
The phase lock threshold registers should be increased when the reference varies too much and the DPLL lock status machine goes in and out of lock while the DPLL tries to keep the loop closed.
The phase lock fill/drain registers determine the speed the DPLL is shown as locked or unlocked. More about them and the thresholds in application note AN-1061.
Phase step limit is used when the DPLL switches references, etc. See AD9545 rev B data sheet, page 89 for more.
Hello,Thank you for your prompt reply.I could understand it very well.Best regards,y-suzuki