ad9528 output skew timing alignment characteristics

Question 1: I try to find out what the variation of two output skews (sysref and dev_clk) could be from boot to boot,sync to sync, temperature changes, between different ad9528?. I need the worst case difference between sysref and dev_clk. Because I need to set a correct timing constraint into the FPGA.

so far I found this table:

Question 2: How can I reduce this skew to a minimum? I will use the PLL1 to SYSREF retimed by PLL1 clock, how can I avoid ending up with the maxium skew of 100 ps?

Question 3: Could this be a one time calibration for each hardware setup?

Question 4: What if I use an external sysref instead of the internal sysref? Which specifications do I need to look at? Or, will this be the same deviation?

  • Q1: it is a configuration that ensures internal zero delay like behavior for the APLL. It is not related in any way to the digital coarse and analog delays.

    Could you tell me how I can enable this "internal zero delay"? I can't find this in the data sheet.

  • 0
    •  Analog Employees 
    on Oct 8, 2020 7:06 PM in reply to JV-IE


    the AD9528 can be configured in such a way to create an "internal zero  delay" like behavior for the APLL.

    The picture above is taken from figure 27, page 25, rev E data sheet. The key detail is that the SYNC command not only resets the dividers from the distribution output block, but also the PLL2 feedback divider N2.

    If I create a configuration that has N2 value equal to the output divider value, then I guarantee the N2 output clock is identical with the OUTx clock. As the N2 output clock is equal to the clock coming from VCXO at the PLL2 PFD level, if I set R1=1 and I disable the doubler before it, I ensure the OUTx clock is equal to the clock at VCXO pins. The behavior is an internal zero delay behavior.