Question 1: I try to find out what the variation of two output skews (sysref and dev_clk) could be from boot to boot,sync to sync, temperature changes, between different ad9528?. I need the worst case difference between sysref and dev_clk. Because I need to set a correct timing constraint into the FPGA.
so far I found this table:
Question 2: How can I reduce this skew to a minimum? I will use the PLL1 to SYSREF retimed by PLL1 clock, how can I avoid ending up with the maxium skew of 100 ps?
Question 3: Could this be a one time calibration for each hardware setup?
Question 4: What if I use an external sysref instead of the internal sysref? Which specifications do I need to look at? Or, will this be the same deviation?
I do not have the skew variation you ask for. I only have what the data sheet states, the typical and the max value.
Regarding the configuration you sent. It should work, but organize the AD9528_1…
Q1: it is a configuration that ensures internal zero delay like behavior for the APLL. It is not related in any way to the digital coarse and analog delays.
The configuration and the SYNC execution…
the AD9528 can be configured in such a way to create an "internal zero delay" like behavior for the APLL.
The picture above is taken from figure 27, page 25, rev E data sheet. The key detail…