Question 1: I try to find out what the variation of two output skews (sysref and dev_clk) could be from boot to boot,sync to sync, temperature changes, between different ad9528?. I need the worst case difference between sysref and dev_clk. Because I need to set a correct timing constraint into the FPGA.
so far I found this table:
Question 2: How can I reduce this skew to a minimum? I will use the PLL1 to SYSREF retimed by PLL1 clock, how can I avoid ending up with the maxium skew of 100 ps?
Question 3: Could this be a one time calibration for each hardware setup?
Question 4: What if I use an external sysref instead of the internal sysref? Which specifications do I need to look at? Or, will this be the same deviation?
I do not have the skew variation you ask for. I only have what the data sheet states, the typical and the max value.
Regarding the configuration you sent. It should work, but organize the AD9528_1…
Q1: it is a configuration that ensures internal zero delay like behavior for the APLL. It is not related in any way to the digital coarse and analog delays.
The configuration and the SYNC execution…
the AD9528 can be configured in such a way to create an "internal zero delay" like behavior for the APLL.
The picture above is taken from figure 27, page 25, rev E data sheet. The key detail…
most probably you obtain the dev_clk from PLL2, not PLL1. If you use PLL1 only to create dev_clk, you are not using the full capability of the AD9528.
So you need to look at the PLL2 numbers from the table you list.
Let me explain the data from the PLL2 outputs:
- PLL2 to PLL2 means between two outputs that come from PLL2 output
- PLL2 to SYSREF means between two outputs, one that comes from PLL2 output and the SYSREF block. Then it depends on how SYSREF is created: retimed by PLL2, not retimed by any clock (so buffered from an external SYSREF) and retimed by PLL1 output.
The max numbers represent the max skew over process, temperature range and voltage supply range. They represent the worst case when the outputs are on the same chip. They do not represent the skew numbers wihen the outputs are from different chips, the reason being that people create both DEVCLK and SYSREF from the same chip. If you have multiple chips, there are ways to synchronize (align) the outputs of one chip with the outputs from another chip. Just tell me exactly what you provide as reference and what you need to obtain and I'll tell you how to proceed.
To reduce the skew to a minimum: I see two choices: one where in production, you calibrate every single AD9528 and use the Digital Coarse and the Analog Fine delays to correct it. The other is to use the typical number from the table above and compensate for it every chip.
If you provide the SYSREF externally, the skew is 620ps typ, 750ps max from the table you list.
Bottom line is what I said above: Just tell me exactly what you provide as reference, what you need to obtain and how many dev_clks and sysrefs and I'll tell you how to proceed.
the amount of skew isn't the issue, it is the variation of the skews that worries me (over process, temperature range and voltage supply range). Fixed skew can easily be compensated once during development.
At this moment I use a 120MHz VXCO, which I am intended to replace with a 240MHz VCXO. This case my Output 12 and Output 13 who serve as the power-up ready clocks fed to the FPGA without reconfiguration. This will simplify the boot process of the FPGA (switching the clock of FPGA logic could result in a meta-stability state). This clock is connected to IBUFDS_GTE4 => BUFG_GT => pl logic. Without interaction of an additional mmcm.
In following diagram contains our digital board (green) with a rf board (with adrv9009 on it) connected to it. The rf boards must be aligned in absolute phase. At this moment I made a configuration with two platform setups, but this must have the option to expand to more platforms.
The extra PLL (AD9528_1) on the rf board acts as phase clean up. This to preserve good phase noise on the dev_clk fed into the adrv9009.
Regarding the configuration you sent. It should work, but organize the AD9528_1 with the PLL2 in this mode below to work in an "internal zero delay" like configuration:
You provide the 240MHz at VCXO_IN and because the OUT0 divider=4, the same value as N2=4, the chip produces 240MHz in phase with the N2 output clock. This clock is identical to the other PFD clock, that is the 240MHz from VCXO. The reason this works is because the SYNC operation resets both the OUT0 divider and the N2 divider.
pminc48 said: "internal zero delay"
Q1: Is this the "digital coarse delay". And not the the analog delay (no skew effect)
pminc48 said:You provide the 240MHz at VCXO_IN and because the OUT0 divider=4, the same value as N2=4, the chip produces 240MHz in phase with the N2 output clock. This clock is identical to the other PFD clock, that is the 240MHz from VCXO. The reason this works is because the SYNC operation resets both the OUT0 divider and the N2 divider.
Q2: Identical clock=> no skew difference? So N2_divider and out0_divider has the same skew? Or only phased locked?
Q3: (If in Q2 N2_divider and out0_divider has the same skew.) Suppose I made the out1_divider=8, would this output have a different skew? And if there is a difference, would this skew be fix?
The configuration and the SYNC execution ensures the clock at the distribution divider output is identical to the VCO clock input at the PFD level. Then the blocks after the divider introduce the skew between the output and the input because they introduce propagation delays. Also the VCXO input suffers a propagation delay until it arrives at PLL1 PFD. See the block diagram, figure 27, page 25, rev E data sheet.
The data sheet does not give the delays each block introduces. It gives the Propagation delay of VCXO path (1.92 ns to 2.7ns) and this includes all the blocks mentioned above, but not individually.
The clocks going through the blocks after the divider suffer propagation delays that vary from output path to output path to create the skew between the outputs
If the distribution divider is a multiple of the PLL1 feedback divider, the output is still aligned to the VCXO input at the PFD level. Then the discussion we had at Q2 applies.
The data sheet does not give any measure of the skew variation in time, so I cannot tell you if the skew is fixed in time or not. We only know the skew varies between the limits in the specifications table. I already provided you with two approaches in dealing with this.
pminc48 said:Q1: it is a configuration that ensures internal zero delay like behavior for the APLL. It is not related in any way to the digital coarse and analog delays.
Could you tell me how I can enable this "internal zero delay"? I can't find this in the data sheet.
The picture above is taken from figure 27, page 25, rev E data sheet. The key detail is that the SYNC command not only resets the dividers from the distribution output block, but also the PLL2 feedback divider N2.
If I create a configuration that has N2 value equal to the output divider value, then I guarantee the N2 output clock is identical with the OUTx clock. As the N2 output clock is equal to the clock coming from VCXO at the PLL2 PFD level, if I set R1=1 and I disable the doubler before it, I ensure the OUTx clock is equal to the clock at VCXO pins. The behavior is an internal zero delay behavior.