ADRV9002_DEV-CLKIN_Requirement

Hi,

We are planning to use the low phase noise 10MHz OCXO for ADRV9002 DEV_CLKIN and it has the sinusoidal output with 50ohm impedance. But ADRV9002 chip will support clipped sinewave only.


1. Pls suggest, how to connect to 50ohm sinusoidal output of OCXO to DEV_CLKIN of ADRV9002 Transceiver chip?
2. In EVM, Transceiver reference clock is given to FPGA. Pls explain, what is the purpose of the reference clock and differentiate the FPGA_REF_CLK and DEV_CLK_OUT ?

Regards

James A

  • Hi,

    Pls reply as soon as possible for trailing query.

    Regards

    James A

  • Hi,

    Pls refer the below query and reply as soon as possible.

    Note: We are in design completion stage

    1. In ADRV9002 EVM power supply circuit section, 3A Ferrite beads are used for all power supply nets. Whether it is required 3A ferrite beads for all nets or i can use the lesser current (<2A) ferrite bead. (Except high current path of VDIG-1P0). Can u share the typical and maximum current of each net?


     With ADRV9002 EVM board, we have done the Rx channel test validation with external clock and clock is given from the signal generator(Sinusoidal input). But in EVM, Fanout buffer part is ADCLK944BCPZ and it is accept the input level as AC or DC coupled LVDS, LVPECL and CMOS only not sinusoidal waveform.


    2. How clock fanout buffer is working with sinusoidal input?


    3. If it is accept the sinusoidal CLKin, can i use the similer series part 8 O/P ADCLK948BCPZ and clock fanout buffer input wiil be from 10MHz OCXO (sinusoidal input) for ADRV9002?


    4. ADRV9002 chip accept the LVDS, Clipped sinewave and CMOS only. Is it possible to give the sinusoidal input ?


    5. ADCLK944BCPZ output voltage level meet the requirement of ADRV9002 input clock amplitude requirement. But clock buffer output has LVPECL output and input of the ADRV9002 is LVDS. Pls clarify?


    6. For TX port interface, input LVDS voltage level is 825mV to 1675mV. As per LVDS standard, voltage level near by 254 to 454mV at differential. Pls clarify?


    7. For Tx port interface, whether the external common mode voltage is required or internally it can be generate?

    Thanks

    James A

  • 0
    •  Analog Employees 
    on Oct 16, 2020 3:20 PM 1 month ago in reply to auxilian.james

    HI,

    I think you should be posting these questions to the RF transceivers community. I do not believe people supporting ADRV9002 monitor this particular EZ section

    Petre