AD9516-1 CLK input from LVDS oscillator

I wanted to get some guidance on using an oscillator with an LVDS output to drive the CLK pins (input clock) on the AD9516-1. The reference design I'm using has a LVPECL oscillator and is configured as an AC-Coupled LVPECL with Parallel Transmission Line (it matches Figure 73 in the AD9516-1 datasheet). 

I'm assuming I can just treat the CLK pins as LVDS input (just 100 ohm termination across the 100 ohm differential pair, like Figure 74 in the datasheet), but I wanted to double check. The datasheet is a little vague in that it just says "Accepts LVPECL, LVDS, or CMOS."

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    •  Analog Employees 
    on Sep 17, 2020 8:57 PM 5 months ago in reply to rdb9879

    HI,

    Let me try an explanation.

    The ADCLK925 revB data sheet states this at page 12:

    The ADCLK925 evaluation board manual shows the 50 ohm terminations that must be used with the oscilloscope probes to sense the output clocks:

    It is as if one has 100 ohm load resistor across the Qx and Qx\ outputs.

    In the schematic you sent, they used the 100 ohm resistor and they added ac coupling capacitors. The reason for these capacitors should be the fact the AD9516-1 introduces its own common mode voltage, so one has to use ac coupling to interface the clock.

    Also, the common mode voltage generated by the ADCLK925 is from figure 7 in the data sheet approximately 1.9V, while the AD9516-1 introduces 1.5V common mode voltage. An additional reason to decouple the clock.

    In the end, what is the problem you need to solve? I think I provided enough guidance on the conditions you need to meet to interface a clock to the AD9516-1.

    Petre