AD9516-1 CLK input from LVDS oscillator

HI,

the figures 73 and 74 you refer to are about the outputs of the AD9516-1. You need to use the CLK, CLK\ specifications:

And the CLK/CLK\ circuit from the eval board:

See what the circuit recommends the LVPECL oscillator from the resistor load perspective and then pass the signals through the ac coupling capacitors. Make sure the amplitude of the signal is more than 150 mV, but less than 2V.

Petre

Can you explain the interface happening in this circuit? This is from the AD9136-FMC-EBZ eval kit.

HI,

Let me try an explanation.

The ADCLK925 revB data sheet states this at page 12:

The ADCLK925 evaluation board manual shows the 50 ohm terminations that must be used with the oscilloscope probes to sense the output clocks:

It is as if one has 100 ohm load resistor across the Qx and Qx\ outputs.

In the schematic you sent, they used the 100 ohm resistor and they added ac coupling capacitors. The reason for these capacitors should be the fact the AD9516-1 introduces its own common mode voltage, so one has to use ac coupling to interface the clock.

Also, the common mode voltage generated by the ADCLK925 is from figure 7 in the data sheet approximately 1.9V, while the AD9516-1 introduces 1.5V common mode voltage. An additional reason to decouple the clock.

In the end, what is the problem you need to solve? I think I provided enough guidance on the conditions you need to meet to interface a clock to the AD9516-1.

Petre