Eval-ad9516-1 CMOS interface

1.I have an ad9516-1 evaluation board. I want to use two cmos interfaces with different frequencies, but the sixth and seventh interfaces on the evaluation board are not soldered. Therefore, I want to solder the sixth and seventh interfaces, but I don’t know how to do it. What should I do?

2.I use the CLK pin to introduce a 20MHZ clock, and then configure the CMOS interface and LVPECL interface. In this process, no internal or external VCO is used, and only ad9516-1 is used as a frequency divider. During the experiment, I found that I had not started the signal generator to send the clock to the CLK pin at the beginning, but through the oscilloscope, I could see an unstable square wave at about 12MHz on the CMOS pin. And I also see some transitions on the LVPECL pin.
After the clock is transmitted, there are sometimes some unstable states on the LVPECL pin.
What caused the above situation and how should we improve the situation?

Thanks

rover

  • 0
    •  Analog Employees 
    on Aug 31, 2020 1:08 PM 5 months ago

    Hi,

    On the first question: the evaluation board has 100 ohm resistors connected between OUT6 and OUT6\ and between OUT7 and OUT7\. Take out the resistors to use these outputs in CMOS mode.

    On the second question: please send me the stp file you used when you did this test. I suppose you or the software generated the sync command which means the outputs were set to generate clocks. If no input clock was provided, there should not be any output clocks. Did you change the schematic of the CLK circuit? Maybe CLK was floating. Put an oscilloscope probe on C46 and C43 AD9516 side of the capacitors to see what is going on.

    Petre 

  • Hello petre
    1. After removing the resistor, solder the output interface, right? But I found that the reserved holes are a little too small, it seems that SMA interface or DuPont cable can not be installed? What should I do?
    In addition, what should be done with the LVPECL interface?
    2. The following is my .stp file, I just sent a 20MHz clock (ad9516-1 does not feed back to the signal generator) to divide the frequency.

    sorry, i can't upload my .stp file,but only the screenshot.

    thanks

    rover

  • 0
    •  Analog Employees 
    on Aug 31, 2020 2:24 PM 5 months ago in reply to rover

    Hi,

    just connect some wires to the OUT6 and OUT7 terminals. The board was simply not done to support CMSO clocks at OUT6 and OUT7. Or test the clocks on another outputs that do have terminals.

    To attach a stp file, I found that if I zip it first, then I am allowed to upload the file.

    Based on the photo you provided, only OUT0  replicates CLK input in LVPECL mode.

    OUT2 generates a clock obtained by dividing CLK by VCO divider. This is OK.

    OUT8, OUT9 are set in a correct way.

    I usually set WRITE command to have the ALL and AUTO boxes checked. The UPDATE command is already with AUTO option set. Try these and they will ensure the chip is set correctly. 

    Petre

  • I have a rubidium clock, the output common mode voltage is about 0V, I want to use the output of this rubidium clock to send to the CLK interface of ad9516-1, can I input it directly? Or what conversion measures I need to go through.

  • 0
    •  Analog Employees 
    on Sep 8, 2020 9:11 PM 5 months ago in reply to rover

    this was responded at: https://ez.analog.com/clock_and_timing/f/q-a/534927/ad9516-1-clk-rubidium-clock/387478#387478

    Please do not post the same question in two different places.

    Petre