Hi!Early we used HMC6832 for continuous clock fanout.But now we also want to use HMC6832 for LVDS data clock fanout for protocol like spi but using LVDS signals. LVDS clock input can interrupt sometimes but then appears again.I want to use next schematic:But I am confused "Min Frequency Range":and capacitors on the Functional Block Diagram:Will I have problem like on the figure (Voltage INP0 minus INN0) due 100pF capacitors:Can HMC6832 miss several first pulses of input clock due 100pF capacitors?
That is correct the internal input capacitors will cause an initial CM ramp if you go from a DC signal to a AC signal. Some of the LTC6954/55/57 buffers do not have this input cap, but the common modes do not necessarily line up with LVDS. So maybe you could put a parallel cap and high value resistor network to work with these parts.
You may want to look at the ADN4670 also.