Application of the ad9545 chip

I'm planning to use the AD9545 is to obtain a stable output frequency for clocking an LTE and 5G station. The expected stability at the output have to be 1 ppb or better.
Description of the circuit.
REF A input - 1pps GPS time stamps is supplied. The SYS IN is supplied with a 52 MHz crystal reference signal. The refB input is driven by a signal from the spare TCXO reference oscillator when the GPS signal is lost. The system signal clock is compensated by 1 pps GPS also.
Questions:
1) Is an output 1 ppb frequency stability really achievable with a 1 pps GPS reference at REFx inputs?
2) How fast a needed accuracy would be achieved when the DPLL Fast Acquisition (FACQ) is activated?
3) Could the AD9542 chip be applied for these purposes?

1pps_input_DPLL0.zip

  • 0
    •  Analog Employees 
    on Aug 14, 2020 6:40 PM

    HI,

    from the file you sent and your description, I see these problems:

    1) "REF A input - 1pps GPS time stamps is supplied.Ypu have to supply a 1PPS analog clock at REFA. You cannot supply time stamps there.

    2) REFB=10MHz and it is provided by a TCXO. 

    3) You want to use a 10 MHz clock at Aux TDC0, but you did not enable any Mx pins to receive the 10 MHz clock. Please tell me what do you want to accomplish with this additional 10 MHz clock, so I can recommend a solution.

    4) DPLL0 is to function in internal zero delay using REFA=1Hz to create 30.72 MHz output. The configuration wizard signals an error. I put it in phase buildout and then back in internal zero delay and it passed. 

    5) DPLL1 is to function in internal zero delay from REFB=10 MHz to create a 30.72MHz clock. This is not possible because 30.72MHz is not an integer multiple of 10 MHz. So I set it in phase buildout (at least until we clarify what you want to do here)

    6) about the system clock compensation settings:You set Aux DPLL to function on REFA to compensate DPLL0, DPLL1 and TDCs. As REFA is used in DPLL), you cannot also compensate it. But you can compensate DPLL1 and TDCs. Then you also selected DPLL0 to compensate DPLL1. This would be good if the Aux DPLL would not compensate DPLL1.

    Bottom line on the cso file you sent: Usually, the TCXO compensates the system clock, so when the 1 PPS disappears, the DPLL enters in holdover and the output is very stable. So you can select AuxDPLL to work based on REFB to compensate DPLL0 and TDCs. I do not get why you would want to use REFA for system clock compensation when this clock may disappear. Then, I suggest thinking to an OCXO instead of a TCXO because of the stability you target.

    The FACQ works only to get the frequency lock faster. The issue is always the phase lock that takes a long time. After power up, the lock is faster is Ref Sync feature is enabled (I enabled it for you).

    The AD9542 does not work for 1 PPS loops.

    I also made some changes in the Lock detector settings of REFA.

    The site does not allow me to attach the cso file I created. I'll try after hitting Reply button

    Petre

  • 0
    •  Analog Employees 
    on Aug 14, 2020 6:42 PM in reply to pminc48

    I'm sorry, for some reason today I cannot attach a file. I tried two browsers

    Petre

  • 0
    •  Analog Employees 
    on Aug 14, 2020 6:45 PM in reply to pminc48

    I put the file here: https://ez.analog.com/clock_and_timing/m/file-uploads/1760

    Hopefully you can access it

    Petre

  • Good day, Petre!
    Thank you very much for such a detailed answer!

    I want to clarify a few points.

    >> "You have to supply a 1PPS analog clock at REFA. You cannot supply time stamps there". 

    I hope I understood you correctly. There was a terminological confusion. At the REFA input, I was going to send a 1pps pulse coming from a GPS receiver.

    >> "I do not get why you would want to use REFA for system clock compensation when this clock may disappear. Then, I suggest thinking to an OCXO instead of a TCXO because of the stability you target."

    Before your answer, I did not fully understand the principle of the microcircuit functioning. Now I have come to the same solution that you suggest.

    >>"The FACQ works only to get the frequency lock faster. The issue is always the phase lock that takes a long time. After power up, the lock is faster is Ref Sync feature is enabled (I enabled it for you)."

    Thank you, I understand you! But I am very interested in the following question:What is the long term frequency stability achievable when used as a 1pps reference?

  • 0
    •  Analog Employees 
    on Aug 17, 2020 5:57 PM in reply to Iliya

    HI,

    not clear to me at what frequency stability you refer to.

    If the 1PPS is provided as reference the AD9545 DPLL remains lock to it as long as this reference is applied.

    When this reference disappears and the system clock is compensated from the OCXO, then the long term stability of the DPLL (which is now in holdover) depends on the long term stability of the OCXO. This data is specified in the  OCXO date sheet.

    Petre