System clock reference input path for AD9544

Hi,

According to the datasheet of AD9544, I have made the following schematic for the system clock input:

R1 = 150R

R2 = 330R

However, I discovered that my TCXO deliver an 0.2Vdd - 0.8Vdd output (https://www.mouser.fr/datasheet/2/122/ECS-2520SMV-1628252.pdf).

And when I observe with the scope, it seems that the level output is smaller than this (output current too high?).

The System clock reference input path specifications specifies that Input voltage must be 0.9V minimal for high level and 0.5v maximal for low level.

When I observe the TCXO output with a scope, I see 0.84V-2.3V (Low - HIGH).

When I observe the XOA input with a scope, I see 930mV-590mV (Low - HIGH).

I tried to put other resistor value as well and I observe the following value for R1=330R , R2=470R :
TCXO output : 0.86V-2.2V
XOA input : 976mV-544mV

Is there any resistor and capacitor adjustement for make the ad9544 works with this TCXO?

Best regards,

Bastien

Top Replies

    •  Analog Employees 
    Jul 22, 2020 in reply to Bastien0530 +1 verified

    Hi,

    AD9545_setup.zip

    I created the attached cso file. You can extract the register values from it. It has the AD9545 name because I created it with the AD9545 plugin. The AD9544 plugin blocks certain AD9544…

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  • 0
    •  Analog Employees 
    on Jul 17, 2020 2:21 PM 8 months ago

    HI,

    I looked over the TCXO data sheet. It has a CMOS output that is function of the supply voltage. I suppose you use 3.3V supply. Let's consider it can vary +/-5%, between 3.135V and 3.465V.

    The TCXO data sheet says VOL=0.2*VDD (max) and VOH=0.8*VDD (min).

    Worst cases: VOL=0.2*3.465=0.693V (max) and VOH=0.8*3.135=2.508V (min).

    We want to bring these values within VIL=0.5V max and VIH=0.9V min. I will use VIH=1V, just to be above 0.9V.

    If in the figure 30 you attached, I call R1, the 330ohm resistor and R2, the 150ohm, I made some quick calculations and if I choose R1=220 ohm and R2=150ohm, the VOH=2.508V is brought down to 1V.

    Try to use these values and please measure the voltages before the ac coupling capacitor. After the capacitor, the chip introduces a 0.75V common mode voltage. Also, in the evaluation software, do not check the XTAL Source box in the configuration wizard:

    For some reason, I cannot paste the figure for you. I'm sorry.

    Petre 

  • Hi,

    First, I would like to thank you for your fast and pertinent reply.

    I tried the values you provided me and when I observed the swing before the capacitance, I measured VOL = 400mV and VOH = 800mV. It seems that the Voltage Output of the CMOS is driven down because of current driven by the resistors. Concerning the XTAL box, I do not use the configuration wizard as I do not have the evaluation board.

    However, I tried configure the device with this swing described below, and it seems that the SYSCLK PLL is stable and OK (register 0x3001=0X03). There is no output at all and when I checked the PLL register, I found out that the DPLL0 was not locked (register 0x3100=0x28, register 0x3101=0x08, register 0x3102=0x02). PPS reference input seems to be OK (register 0x3005=0x10).

    My application aim at produce 4MHz differential output from PPS single ended input on REFA. In order to achieve that I realized a C program which makes the following configurations.

    0x0200=5E	//SYSCLK
    0x0201=00
    0x0202=00
    0x0203=BA
    0x0204=1D
    0x0205=D2
    0x0206=05
    0x0207=32
    
    0x0300=A0	//GENERALA
    
    0x0400=00	//REFA
    0x0401=00
    0x0402=00
    0x0403=00
    0x0404=00
    0x0405=00
    0x0406=64
    0x0407=A7
    0x0408=B3
    0x0409=B6
    0x040A=E0
    0x040B=0D
    0x040C=A0
    0x040D=86
    0x040E=01
    0x040F=03
    0x0410=0A
    0x0411=00
    0x0412=00
    0x0413=00
    0x0414=00
    
    0x1000=10	//DPLL0
    0x1001=93
    0x1002=2B
    0x1003=88
    0x1004=C9
    0x1005=15
    0x1006=FF
    0x1007=FF
    0x1008=FF
    0x1009=00
    
    
    0x1080=14	//APLL0
    0x1081=E0
    
    0x10D7=01
    
    0x1200=03	//TRANSLATION PROFILE 0.0
    0x1201=00
    0x1202=04
    0x1203=00
    0x1204=2C
    0x1205=1A
    0x1206=00
    0x1207=00
    0x1208=00
    0x1209=00
    0x120A=00
    0x120B=00
    0x120C=FF
    0x120D=C1
    0x120E=EB
    0x120F=0E
    0x1210=00
    0x1211=00
    0x1212=00
    0x1213=00
    0x1214=00
    
    0x2103=1C
    0x2104=1C
    0x2203=1C

    I hope you could help me,

    Bastien

  • 0
    •  Analog Employees 
    on Jul 22, 2020 2:31 PM 8 months ago in reply to Bastien0530

    HI,

    sorry for the delay in responding to you.

    I recommend using the evaluation software in offline mode anyway. It is very hard in my view to configure the AD9544 properly without it. The software creates a .cso file and then you extract from it the registers values and you use them on your board.

    If you tell me exactly the configuration you want to target (reference frequencies, how you want to create the system clock, the output frequencies, in what mode you want to use the DPLLs), I can make it for you. 

    Petre

  • Hi,

    I did not know that we could use the evaluation software without the devboard, that is great, thank you so much.

    My final configuration should be the following:

    SYSCLK : TCXO 25MHz

    REFA : single ended 1.8V CMOS PPS

    REFB : single ended 1.8V CMOS PPS (priority higher than REFA)

    OUTA : 4MHz differential LVDS output (see schematic)

    OUTB : 32KHz differential LVDS output (see schematic)

    DPLL : which is the better mode for a fast acquisition and output synchronization with input?

    Thank you for your reply,

    Bastien

  • +1
    •  Analog Employees 
    on Jul 22, 2020 6:04 PM 8 months ago in reply to Bastien0530

    Hi,

    AD9545_setup.zip

    I created the attached cso file. You can extract the register values from it. It has the AD9545 name because I created it with the AD9545 plugin. The AD9544 plugin blocks certain AD9544 features.

    I do not recommend to use a 25 MHz TCXO as the system clock source. I recommend using a regular 52 MHz crystal resonator instead, connect the 25 MHz TCXO at REFAA (for example) and use it to compensate the stability of the system clock. The system clock will be as stable as the TCXO (see System Clock compensation section in the AD9545 rev B data sheet page 137 and section Compensation Method 3 at page 142).

    The configuration uses DPLL0 in internal zero delay mode to create OUT0A=4MHz and OUT0B=32 kHz. I created 2 profiles, one using REFA=1Hz, the other using REFB=1Hz.

    I enabled the system clock compensation using the auxiliary DPLL with a 50 Hz bandwidth and compensating DPLL0 and TDCs.

    Use the evaluation board schematic as a reference for your schematic. You can find it here:

    https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9545.html

    Petre

  • Hi Petre,

    Thank you so much for your help, I make it finally works using evaluation software for generate configuration.

    I take note of your recommendations for the next version of schematic. I will also keep your configuration file for this future architecture.

    Great support, thank again!

    Bastien

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