How much drift do the AD9547, AD9548, and AD9549 devices exhibit when in holdover mode?
The quick answer is - they add nothing to the drift; they will drift as little or a smuch as the system clock reference source.
The devices you called out rely on an external system timing source to clock the digital elements of a PLL. When the devices go into holdover, this system timing reference becomes the time base source and the devices essentially run like a direct digital synthesizer (DDS). In a DDS, the output frequency has a direct, rational relationship to the system timing clock frequency. This relationship is established with digital elements that do not drift over time, temperature, or voltage, so there is not even a slight difference between the relative drift that occurs on the system timing source versus that of the output.