I am wanting to use an ADN2816 clock and data recovery chip as the clock source for an ADC. I need 0.4 ps jitter. The ADN2816 makes great play of using a dual PLL architecture and filter to achieve very low jitter generation and good jitter attenuation above the cutoff frequency.
However all the jitter specs are in UI (unit intervals), based on a particular clock frequency. This suggests that generated jitter is proportional to operating frequency. Looking at other similar devices jitter plots this might not be so (for example a MAX3872 CDR also specified in UI, shows 1.6ps rms jitter at 2.488 Gbps and 2.2ps rms at 622 Mbps. Jitter clearly does not scale with frequency - maybe more with slew rate).
So I would be very grateful if someone could give me the jitter in absolute ps, not some relative value for the magical ADN2816. I'd be thinking that the recovered clock jitter plots shown in the Maxim data sheet would be very useful in the AD data sheets as well.
Thanks for your help!
- Bart Schroder