What is jitter of ADN2816 output in ps?

Hello,

I am wanting to use an ADN2816 clock and data recovery chip as the clock source for an ADC. I need 0.4 ps jitter. The ADN2816 makes great play of using a dual PLL architecture and filter to achieve very low jitter generation and good jitter attenuation above the cutoff frequency.

However all the jitter specs are in UI (unit intervals), based on a particular clock frequency. This suggests that generated jitter is proportional to operating frequency. Looking at other similar devices jitter plots this might not be so (for example a MAX3872 CDR also specified in UI, shows 1.6ps rms jitter at 2.488 Gbps and 2.2ps rms at 622 Mbps. Jitter clearly does not scale with frequency  - maybe more with slew rate).

So I would be very grateful if someone could give me the jitter in absolute ps, not some relative value for the magical ADN2816. I'd be thinking that the recovered clock jitter plots shown in the Maxim data sheet would be very useful in the AD data sheets as well.

Thanks for your help!

- Bart Schroder

  • 0
    •  Analog Employees 
    on Aug 10, 2011 9:30 PM

    Hi Bart,

    >However all the jitter specs are in UI (unit intervals), based on a  particular clock frequency.

    We did it this way so that we're consistent with the Telcordia GR-253 core spec. Here's an excerpt:

    > This suggests that generated jitter is  proportional to operating frequency.

    Yes and no. The jitter limits (in ps) in GR-253 scale with UI, which is inversely proportional with operating freqeuncy.

    > Looking at other similar devices  jitter plots this might not be so (for example a MAX3872 CDR

    > also  specified in UI, shows 1.6ps rms jitter at 2.488 Gbps and 2.2ps rms at  622 Mbps.

    > Jitter clearly does not scale with frequency  - maybe more  with slew rate).

    There are a lot of factors involved there. Yes, it's possible if the part is starting to be limited by (as you mention) slew rate, etc.

    > So I would be very grateful if someone could give me the jitter in  absolute ps,

    > not some relative value for the magical ADN2816.

    1 UI at OC-3 is 1/155Mbps = 6.43ns, so 1 mUI = 6.43 ps.

    1 UI at OC-12 is 1/622Mbps ~ 1.6ns, so 1 mUI = 1.6 ps.

    In Table 2 of the datasheet, we have:

    Standard     Typ     Max         

    OC-3          1 mUI     2 mUI

    OC-12        1 mUI     3 mUI

    I think the typical numbers mentioned above are probably rounded as they exceed the specifications (usually 10 mUI) by such a large margin.

    Standard    Typ          Max         

    OC-3          6.43ps     12.8ps, RMS (integrated from 12kHz to 1.3 MHz.)

    OC-12        1.6ps         5.4ps, RMS (integrated from 12kHz to 5 MHz.)

    As a comparison, at the OC12 data rate: 622.08Mbps, our ADN2816 jitter generation is about 1.6pS, rms, which is much better than the 2.2pS, rms specified for MAX3872.

    > I'd be  thinking that the recovered clock jitter plots shown in the Maxim data  sheet would be very useful in the AD data sheets as well.

    I'll pass along the request about recovered jitter plots to the applications team.

    -Paul Kern

  • Hi Paul,

    Thanks very much for taking the time to answer me, and thinking about it.

     

    I do understand that for the Tecordia spec requirements the part has oceans of head room, and so specing it in terms of mUI makes sense.

    However I want to use it to clock an ADC, and here mUI, especially when it is rounded up, is not such a useful indicator of performance.  My attention was drawn to the part because of the obvious attention to jitter. 

     

    But I guess the maximum values of 2 and 3 mUI do indicate that jitter will exceed 1 mUI, and so I should use the values you have given, which sadly are not good enough on their own. Further reading of the data sheet does confirm to me that the architecture could be doing this.

     

    If you happened to know of a CDR that operates at 125 or 250 MHz with better jitter, I would be very grateful! Ideally I need 0.4 ps rms.

     

    Thanks again for your help.

     

    Kind regards

     

    Bart Schroder

    Cleverscope.

     

     

    From: pkern analog@sgaur.hosted.jivesoftware.com

    Sent: Thursday, 11 August 2011 05:31

    To: Bart Schroder

    Subject: New message: "What is jitter of ADN2816 output in ps?"

     

    <http://ez.analog.com/index.jspa> Analog Devices EngineerZone

    What is jitter of ADN2816 output in ps?

    reply from pkern <http://ez.analog.com/people/pkern>  in Clock and Timing - View the full discussion <http://ez.analog.com/message/30288#30288

  • 0
    •  Analog Employees 
    on Aug 11, 2011 1:58 PM

    Hi Bart,

    Please send me your email address. Mine is paul.kern@analog.com. I'm going to forward it to the right person at Analog who should be able to get you the exact data.

    -Paul Kern

  • 0
    •  Analog Employees 
    on Aug 2, 2018 4:14 PM
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