AD9513 input

Hello,

I would like to use the AD9513 CLK input as single-ended, however, according to the datasheet: "the input level should be 150mVpp to no more than 2Vpp. Anything greater can result in turning on the protection diodes on the input pins".

My question is the following, which kind of TCXO can I use to provide a 40MHz clock input to the AD9513? one with clipped sine output (0.8Vpp), or one with 3.3V LVCMOS output? I would like to make a direct connection betwen the TCXO and the AD9513. Theoretically, the CMOS solution does not fit within the 2Vpp limit. On the other hand, what about clipped sine, won't I have jitter problems due to slew rate requirements at the AD9513 input?

Thanks in advance.

Regards

  • 0
    •  Analog Employees 
    on Feb 20, 2012 7:32 AM

    Dear fvazquez,

    You can use a voltage divider and a TCXO with a 3.3V CMOS output. For a diagram of how to do this, refer to the "Input/Output Termination Recommendations" section of the AD9557 datasheet:

    http://www.analog.com/static/imported-files/data_sheets/AD9557.pdf

    -Paul Kern

  • Dear Paul,

    indeed, that is a straightforward solution for the TCXO with a 3.3V CMOS output. I should just take care of the input/output impedances of TCXO and AD9513, respectively.

    Regarding the clipped sine output TCXO, do you think it may degrade the jitter performance at the AD9513 outputs? according to the AD9513 datasheet, the slew rate of CLKIN should be greater than 1V/ns, which may not be fulfilled if I use a 0.8Vpp clipped sine at 40MHz.

    F. Vázquez

  • 0
    •  Analog Employees 
    on Feb 20, 2012 6:35 PM

    Dear F. Vazquez,

    > indeed, that is a straightforward solution for the TCXO with a 3.3V CMOS output.

    > I should just take care of the input/output impedances of TCXO and AD9513, respectively.

    Yes. However, a perfect impedance match isn't necessary. We have found that the values in the AD9557 datasheet work well, and strike a good balance between a have a strong drive to overcome parasitics, but not pulling too much current out of the CMOS driver.

    > Regarding the clipped sine output TCXO, do you think it may degrade the jitter performance

    > at the AD9513 outputs? according to the AD9513 datasheet, the slew rate of CLKIN should

    > be greater than 1V/ns, which may not be fulfilled if I use a 0.8Vpp clipped sine at 40MHz.

    Correct. You'll have better performance with the CMOS output.