fractional frequency synthesis with AD9510

hello Guys...

Just to confirm, Can AD9510 Generation fractional frequency?

How about the performance (phase noise and spurius) in this mode?

My project is:

ref in: 0.625 or 20 MHz

output frequency 1: 117.5 MHz

output frequency 2: 117.5 MHz+ dozens of Hz or hundreds of Hz, ex: 117.500120XXX, or 117.500085XXX, and so on...

Best Regards

Fernando Henrique Cardoso

Beam Diagnostics Group (DIG)

Brazilian Synchrotron Light Laboratory (LNLS/CNPEM)

Campinas - Brazil - P.O.Box 6192 - ZIP Code 13083-970

Tel: +55 19 3512-1144 / +55 19 82156023

  Fax: +55 19 3512-1004

  • The AD9510 is an Int-N only PLL. However, the AD9552 or the AD9557/8 can accomplish the requested translations.

  • The frequency planning for AD9510 is based in the follow equation:

    FVCO= (ref in/R)x (PB+A)

    where: P is the prescaler and can assume some values like: 2/3, 4/5, 8/9,16/17 and 32/33

    B is a 2^13 counter, A is a 2^6 counter and R is a 2^14 counter.

    imagine the follow examples:

    ref in = 20 MHz,  P=32/33,    B=7136,   A=1,   R=1178

    the frequency will be: 117.5001286207  MHz

    am I right?

  • FVCO= (ref in/R)x (PB+A)

         True. This is still an integer-N translation. Please also keep in mind the limitations of the part, the CLK in only has the bandwidth to accept a 1.6 GHz signal max.

    where: P is the prescaler and can assume some values like: 2/3, 4/5, 8/9,16/17 and 32/33

    B is a 2^13 counter, A is a 2^6 counter and R is a 2^14 counter.

         True

    imagine the follow examples:

    ref in = 20 MHz,  P=32/33,    B=7136,   A=1,   R=1178

    20e6 / 1178 = 16.978kHz

    16.978kHz * (32 * 7136+1) = 3.876961 GHz

    3.876961 GHz / 33 = 117.483665175 MHz

    Due to frequency limitations within the part, the frequency flexibility of this device is limited from ideal. To achieve the frequency flexibility that you are requesting, I would recommend the AD9552 or AD9557 which implement an actual Frac-N translation using a 20-bit SDM and 24- bit SDM respectively.

  • I am assuming B was supposed to =7137, which would yield:

    ref in = 20 MHz,  P=32/33,    B=7137,   A=1,   R=1178

    20e6 / 1178 = 16.978kHz

    16.978kHz * (32 * 7137+1) = 3.877504 GHz

    3.877504 GHz / 33 = 117.500128621 MHz

    Despite the validity of the math with the corrected B value, the translation is invalid because of the out of spec Fvco and the output divider exceeds a divide by 32. You may be able to reconfigure the device with a valid frequency translation, however the AD9510's architecture is not optimum for the requests you are making.

  • Hello Neil

    Thanks for your answers, was very useful. Let me do some comments:

    1- I used the word "fractional synthesis" in a wrong way. Now I understand my mistake.  I was using fractional synthesis because prescaler assumes some fraction value. Sorry for my mistake.

    2- The math was wrong I used the wrong value for B counter. the correct value for B counter is 7137. Thanks to find this error...

    I will explain my application and you could understand what I am trying to do. :-)

    We are designing a 4 channel ADC board - 130 MSPS maximum. The input signal for these ADCs will be 500 MHz, for this reason the jitter is very important for us.

    to generate the sampling frequency we have a reference freq. of 0.625 KHz, not just this frequency could be used, any  multiple could be used, let’s assume 20 MHz. Using a PLL we can lock the ADC´s sampling frequency with reference. The ADC´s main frequency will be 117.5 MHz. Besides generate the 117.5 MHz, we want sometimes change this frequency a litle bit, putting a kind of frequency offset of dozens of Hertz... The absolute value of this offset does not matter, could be any number in steps of dozens of Hz, and there is no problem is the step is not the same for  all changes... We have apply this frequency offset because we have some frequencies in our signal that could generate aliasing into the BW, so if we change a litle bit the sampling frequency we can optimize our signal processing. 

    OK for this reason we think that the best option (in terms of jitter or close in phase noise) is a low noise PLL with external VCXO, instead a PLL with on-chip VCO or a frequency synthesizer like AD9552 or 9557.  Am I right assuming that?

    I would like to use a VCXO CVHD-950 from Crystek in a frequency of 117.5 MHz. using the 20 ppm of APR.So, I am able to tunning the VCXO up to +-2.35 KHz, So that offset frequency is possible. I will use just use N (P,B and A) and R. I will bypass the output divider.

    About your comments, I did not understand where I am making mistakes…

    So again, thank you very much… if you have any comment, I will appreciate.

    Best regards