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AD9524 Bypass PLL2 mode?

I've looked through and searched the AD9524 register documentation.  I can find no reference to a bypass PLL2 mode but somehow my device seems to be in this mode.  I'm using the eval. board to control the AD9524 in my design by jumpering over the 4 SPI lines and resetb.  This works fine and I have full control through the eval software.  However, my output frequency is not what is expected or what is reported by the eval SW.  I have a 125 MHz VCXO.  I'm targeting for a 4 GHz VCO to divide to 1 GHZ and then to 40 MHz with /25 each output divider.  Instead I'm getting a solid 5 MHz that does not change no matter what I do to PLL2.  This happens on output4 not just output0 and output1 so it is not the bypass mux available for these output[0,1].  Changing the VCO frequency by changing the N divider or doubler as no effect on the output frequency.  Syncing the output dividers, resetting the device and reloading the stp file, powering down/up PLL2 all these have no effect.  The frequency remains unchanged at 5 MHz which is 125/25


I have also discovered a bug with the eval software.  When I click on the output3 control icon the program crashes and aborts.  I tried this several times with the same result.  I ended up having to manually edit my stp file just to set the output to the proper mode.

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