AD9524 Bypass PLL2 mode?

I've looked through and searched the AD9524 register documentation.  I can find no reference to a bypass PLL2 mode but somehow my device seems to be in this mode.  I'm using the eval. board to control the AD9524 in my design by jumpering over the 4 SPI lines and resetb.  This works fine and I have full control through the eval software.  However, my output frequency is not what is expected or what is reported by the eval SW.  I have a 125 MHz VCXO.  I'm targeting for a 4 GHz VCO to divide to 1 GHZ and then to 40 MHz with /25 each output divider.  Instead I'm getting a solid 5 MHz that does not change no matter what I do to PLL2.  This happens on output4 not just output0 and output1 so it is not the bypass mux available for these output[0,1].  Changing the VCO frequency by changing the N divider or doubler as no effect on the output frequency.  Syncing the output dividers, resetting the device and reloading the stp file, powering down/up PLL2 all these have no effect.  The frequency remains unchanged at 5 MHz which is 125/25

.

I have also discovered a bug with the eval software.  When I click on the output3 control icon the program crashes and aborts.  I tried this several times with the same result.  I ended up having to manually edit my stp file just to set the output to the proper mode.

  • 0
    •  Analog Employees 
    on Aug 20, 2012 10:12 PM

    Dear Nlanier,

    > I'm targeting for a 4 GHz VCO to divide to 1 GHZ and then to 40 MHz with /25 each

    > output divider.  Instead I'm getting a solid 5 MHz that does not change no matter

    > what I do to PLL2.  This happens on output4 not just output0 and output1 so it is not the

    > bypass mux available for these output[0,1].  Changing the VCO frequency by changing

    > the N divider or doubler as no effect on the output frequency.  Syncing the output dividers,

    > resetting the device and reloading the stp file, powering down/up PLL2 all these have no effect. 

    > The frequency remains unchanged at 5 MHz which is 125/25

    What happens if you change the output divider?  If we can be absolutely sure of the VCO2 frequency, we can figure out what's happening. My suspicion is that PLL isn't locking, and we need to understand why.

    Here are a few other things to check:

    1. Can you make the AD9524 on the eval board lock?

    2. Are you calibrating VCO2?

    3. Can you see a buffered 125 MHz coming out of the D divider? If you do, then you know that the 125 MHz is getting to PLL2.

    > I have also discovered a bug with the eval software.  When I click on the output3 control icon the program crashes and aborts.  I tried this several times with the same result.  I ended up having to manually edit my stp file just to set the output to the proper mode.

    Please send me your setup file.

    -Paul Kern

  • 0
    •  Analog Employees 
    on Aug 2, 2018 4:37 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin