AD9524 PLL2 don't lock at low temperature

Hi All !!!

I'm using AD9524 PLL2 to generate 5 clocks 64MHz from 32MHz cristal oscillator. All work fine at my table. But I have problem in heat chamber at low temperature.

When AD9524 is locked at -10 degrees, for example and cool up to -40 degrees all work fine, but when AD9524 is power on at -40 degrees PLL2 don't lock at all %(. And need to warm up AD9524 to -20 degrees to bring it work again.

PLL2 settings is

Loop BW 251kHz, Phase Margin 65.2deg, Zero Loc 63.7kHz, PoleLock 1.38MHz, Last Pole Lock 67MHz.

Cristal oscilator i using is Rakon TXO725E with specified working temperature is -40...+85. AD9524 specified working temperature is -40...+85 too, but it don't worked. What i do wrong ?

Thanks a lot!!!


  • 0
    •  Analog Employees 
    on Sep 11, 2012 6:20 PM over 8 years ago

    Hello Denis,

    When powered on at -40C was a VCO calibration done as outlined in data sheet?

    I would read back the status registers to verify that VCXO signal is present.


  • Hello Matt!!!

    There is my startup AD9524 sequence (first digit is register address, second is register value. Update_IO bits flip-flop is not shown)

    0x000 = 0x24 - soft reset

    0x233 = 0x00 - PLL's and output ports on

    0x22C check bits 7 (PLL2 reference clock) & 5 (VCXO enable) ~= 0xA0

    0x01A = 0x00 - CMOS VCXO

    0x1BA = 0x00 - disable PLL1 signals

    0x1BB = 0x80 - disable PLL1_OUT port

    0x0F0       = 0xFE      - charge pump

    0x0F1       = 0x0F      - set divider 60 before PFD

    0x0F2       = 0x23      - doubler on & set charge pump mode

    0x0F4       = 0x06      - set VCO divider

    0x0F6-0x0F5 = 0x00ED    - set PLL filters

    0x0F3       = 0x08      - set switchover & prepare to VCO calibration

    0x0F3       = 0x0À      - VCO calibration on

    0x22D check & wait bit 0 (VCO calibration in progres)

    0x0F3       = 0x08      - VCO calibration off

    0x22C check bits 7 (PLL2 reference clock) & 5 (VCXO enable) & 1 (Lock detect PLL2) ~= 0xA2

    0x196           = 0x08    - channel 0 CMOS

    0x197-0x198     = 0x0005  - channel 0 divider

    0x199           = 0x02    - channel 1 LVDS

    0x19A - 0x19B   = 0x0005  - channel 1 divider

    0x19C           = 0x02    - channel 2 LVDS

    0x19D - 0x19E   = 0x0005  - channel 2 divider

    0x19F           = 0x02    - channel 3 LVDS

    0x1A0 - 0x1A1   = 0x0005  - channel 3 divider

    0x1AE           = 0x02    - channel 4 LVDS

    0x1BF - 0x1B0   = 0x0005  - channel 4 divider

    0x1B1 = 0x20    - channel 5 off


    0x232 = 0x01    - sync channel on

    0x232 = 0x00    - sync channel off

    When temperature is higher or equal -25 degrees readback register 0x22C is 0xA2, registers 0x22D is 0x08.

    But in more cooling condition & start at low temperature 0x22C value is 0xA0, 0x22D is 9x08.

    As i think VCO calibration is done well.


  • Hi all! I have spend a lot of time with my board in heat chamber and i saw the reason of such AD9524 behaviour.

    Usign osciloscope i control LF2_EXT_CAP ad9524 pin and see that voltage at this pin move from 800 mV to 560 mV when cooling. But at -25 degrees this voltage jump suddenly to voltage level 0 or 1.71 V (defined from PLL2 charge pump mode settings).

    And no reinit ot recalibration procedure can't move this level to working mode. Only heating AD9524 up to -25 degrees can do this %( I tried different loop filter settings, but it was no purpose.

    As i understatnd PLL2 feedback can't work at low temperature, becouse there is problem with PD & LF.

    Is AD managers cunning when tell that AD9524 temperature range is −40°C to +85°C?


  • 0
    •  Analog Employees 
    on Sep 12, 2012 9:26 PM over 8 years ago

    Hello Denis,

    You read register 22C after the VCO calibration and get 0xA2

    0x22C check bits 7 (PLL2 reference clock) & 5 (VCXO enable) & 1 (Lock detect PLL2) ~= 0xA2

    This tells me you have no reference into PLL1 and PLL1 is unlocked. 

    Also that there is no feedback signal from PLL2 but PLL2 shows locked. This does not make sense, PLL2 can not be locked without a feedback clock.

    Would it be possible to attach your complete *.stp file?  We can test it in our lab.


  • Thanks for you answer Matt!!!  

    Code comment for my colleague-programmer is not well-defined for everybody %)

    symbol ~= mean than good 0x22C code must look like 1x1x_xx1x. Using Table 53. Readback Registers (Readback 0 and Readback 1) of AD documentation it means :

    7  Status PLL2 reference clock  1: OK

    5  Status VCXO  1: OK

    1  Lock detect PLL2  1: locked

    ie 0xA2 code is "all fine"  code.

    I don't using PLL1 at all, becouse i use Rakon Temperature Compensated Crystal Oscillators TXO732, and assign this Oscillator to OSC_IN througth logic to convert clipped sinus clock to digital clock. That is why i don't need to control PLL1 lock signal.

    Unfortunately I don't have AD9524 evaluation board. All expiremenst done on my board (telecomunication modem). I can send you *.clk file from ADIsimCLK software version 1.40.99, pdf of my schematic file, and sequence for AD9524 initialization. Can you get me your e-mail?

    We get 50 AD9524 from Russian local AD distributor and i think that AD 9524 is not failed. Nowtime I have assembled 4 board's with same low temperature symptoms %(